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@@ -1193,11 +1193,12 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
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intel_encoder);
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intel_encoder);
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}
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}
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-void intel_ddi_set_pipe_settings(struct intel_crtc *crtc)
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+void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
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{
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{
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+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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- enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
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+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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int type = intel_encoder->type;
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int type = intel_encoder->type;
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uint32_t temp;
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uint32_t temp;
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@@ -1205,7 +1206,7 @@ void intel_ddi_set_pipe_settings(struct intel_crtc *crtc)
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WARN_ON(transcoder_is_dsi(cpu_transcoder));
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WARN_ON(transcoder_is_dsi(cpu_transcoder));
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temp = TRANS_MSA_SYNC_CLK;
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temp = TRANS_MSA_SYNC_CLK;
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- switch (crtc->config->pipe_bpp) {
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+ switch (crtc_state->pipe_bpp) {
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case 18:
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case 18:
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temp |= TRANS_MSA_6_BPC;
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temp |= TRANS_MSA_6_BPC;
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break;
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break;
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@@ -1225,10 +1226,12 @@ void intel_ddi_set_pipe_settings(struct intel_crtc *crtc)
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}
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}
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}
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}
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-void intel_ddi_set_vc_payload_alloc(struct intel_crtc *crtc, bool state)
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+void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
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+ bool state)
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{
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{
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+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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- enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
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+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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uint32_t temp;
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uint32_t temp;
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temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
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temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
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if (state == true)
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if (state == true)
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@@ -1238,12 +1241,13 @@ void intel_ddi_set_vc_payload_alloc(struct intel_crtc *crtc, bool state)
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I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
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I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
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}
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}
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-void intel_ddi_enable_transcoder_func(struct intel_crtc *crtc)
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+void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state)
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{
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{
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+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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enum pipe pipe = crtc->pipe;
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enum pipe pipe = crtc->pipe;
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- enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
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+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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int type = intel_encoder->type;
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int type = intel_encoder->type;
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uint32_t temp;
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uint32_t temp;
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@@ -1252,7 +1256,7 @@ void intel_ddi_enable_transcoder_func(struct intel_crtc *crtc)
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temp = TRANS_DDI_FUNC_ENABLE;
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temp = TRANS_DDI_FUNC_ENABLE;
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temp |= TRANS_DDI_SELECT_PORT(port);
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temp |= TRANS_DDI_SELECT_PORT(port);
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- switch (crtc->config->pipe_bpp) {
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+ switch (crtc_state->pipe_bpp) {
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case 18:
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case 18:
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temp |= TRANS_DDI_BPC_6;
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temp |= TRANS_DDI_BPC_6;
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break;
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break;
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@@ -1269,9 +1273,9 @@ void intel_ddi_enable_transcoder_func(struct intel_crtc *crtc)
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BUG();
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BUG();
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}
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}
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- if (crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
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+ if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
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temp |= TRANS_DDI_PVSYNC;
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temp |= TRANS_DDI_PVSYNC;
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- if (crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
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+ if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
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temp |= TRANS_DDI_PHSYNC;
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temp |= TRANS_DDI_PHSYNC;
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if (cpu_transcoder == TRANSCODER_EDP) {
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if (cpu_transcoder == TRANSCODER_EDP) {
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@@ -1282,8 +1286,8 @@ void intel_ddi_enable_transcoder_func(struct intel_crtc *crtc)
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* using motion blur mitigation (which we don't
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* using motion blur mitigation (which we don't
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* support). */
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* support). */
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if (IS_HASWELL(dev_priv) &&
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if (IS_HASWELL(dev_priv) &&
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- (crtc->config->pch_pfit.enabled ||
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- crtc->config->pch_pfit.force_thru))
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+ (crtc_state->pch_pfit.enabled ||
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+ crtc_state->pch_pfit.force_thru))
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temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
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temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
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else
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else
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temp |= TRANS_DDI_EDP_INPUT_A_ON;
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temp |= TRANS_DDI_EDP_INPUT_A_ON;
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@@ -1301,20 +1305,20 @@ void intel_ddi_enable_transcoder_func(struct intel_crtc *crtc)
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}
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}
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if (type == INTEL_OUTPUT_HDMI) {
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if (type == INTEL_OUTPUT_HDMI) {
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- if (crtc->config->has_hdmi_sink)
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+ if (crtc_state->has_hdmi_sink)
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temp |= TRANS_DDI_MODE_SELECT_HDMI;
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temp |= TRANS_DDI_MODE_SELECT_HDMI;
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else
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else
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temp |= TRANS_DDI_MODE_SELECT_DVI;
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temp |= TRANS_DDI_MODE_SELECT_DVI;
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} else if (type == INTEL_OUTPUT_ANALOG) {
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} else if (type == INTEL_OUTPUT_ANALOG) {
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temp |= TRANS_DDI_MODE_SELECT_FDI;
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temp |= TRANS_DDI_MODE_SELECT_FDI;
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- temp |= (crtc->config->fdi_lanes - 1) << 1;
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+ temp |= (crtc_state->fdi_lanes - 1) << 1;
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} else if (type == INTEL_OUTPUT_DP ||
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} else if (type == INTEL_OUTPUT_DP ||
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type == INTEL_OUTPUT_EDP) {
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type == INTEL_OUTPUT_EDP) {
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temp |= TRANS_DDI_MODE_SELECT_DP_SST;
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temp |= TRANS_DDI_MODE_SELECT_DP_SST;
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- temp |= DDI_PORT_WIDTH(crtc->config->lane_count);
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+ temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
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} else if (type == INTEL_OUTPUT_DP_MST) {
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} else if (type == INTEL_OUTPUT_DP_MST) {
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temp |= TRANS_DDI_MODE_SELECT_DP_MST;
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temp |= TRANS_DDI_MODE_SELECT_DP_MST;
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- temp |= DDI_PORT_WIDTH(crtc->config->lane_count);
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+ temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
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} else {
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} else {
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WARN(1, "Invalid encoder type %d for pipe %c\n",
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WARN(1, "Invalid encoder type %d for pipe %c\n",
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intel_encoder->type, pipe_name(pipe));
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intel_encoder->type, pipe_name(pipe));
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@@ -1478,22 +1482,23 @@ static u64 intel_ddi_get_power_domains(struct intel_encoder *encoder)
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return 0;
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return 0;
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}
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}
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-void intel_ddi_enable_pipe_clock(struct intel_crtc *crtc)
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+void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state)
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{
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{
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+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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enum port port = intel_ddi_get_encoder_port(intel_encoder);
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- enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
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+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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if (cpu_transcoder != TRANSCODER_EDP)
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if (cpu_transcoder != TRANSCODER_EDP)
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I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
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I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
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TRANS_CLK_SEL_PORT(port));
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TRANS_CLK_SEL_PORT(port));
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}
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}
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-void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
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+void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
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{
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{
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- struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
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- enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
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+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
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+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
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if (cpu_transcoder != TRANSCODER_EDP)
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if (cpu_transcoder != TRANSCODER_EDP)
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I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
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I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
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@@ -1759,23 +1764,21 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
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struct intel_crtc_state *pipe_config,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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struct drm_connector_state *conn_state)
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{
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{
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- struct drm_encoder *encoder = &intel_encoder->base;
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- struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
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int type = intel_encoder->type;
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int type = intel_encoder->type;
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if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
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if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
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intel_ddi_pre_enable_dp(intel_encoder,
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intel_ddi_pre_enable_dp(intel_encoder,
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- crtc->config->port_clock,
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- crtc->config->lane_count,
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- crtc->config->shared_dpll,
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- intel_crtc_has_type(crtc->config,
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+ pipe_config->port_clock,
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+ pipe_config->lane_count,
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+ pipe_config->shared_dpll,
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+ intel_crtc_has_type(pipe_config,
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INTEL_OUTPUT_DP_MST));
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INTEL_OUTPUT_DP_MST));
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}
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}
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if (type == INTEL_OUTPUT_HDMI) {
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if (type == INTEL_OUTPUT_HDMI) {
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intel_ddi_pre_enable_hdmi(intel_encoder,
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intel_ddi_pre_enable_hdmi(intel_encoder,
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pipe_config->has_hdmi_sink,
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pipe_config->has_hdmi_sink,
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pipe_config, conn_state,
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pipe_config, conn_state,
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- crtc->config->shared_dpll);
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+ pipe_config->shared_dpll);
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}
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}
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}
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}
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@@ -1922,8 +1925,7 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config,
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struct intel_crtc_state *pipe_config,
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struct drm_connector_state *conn_state)
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struct drm_connector_state *conn_state)
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{
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{
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- struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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- uint8_t mask = intel_crtc->config->lane_lat_optim_mask;
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+ uint8_t mask = pipe_config->lane_lat_optim_mask;
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bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
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bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
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}
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}
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