|
@@ -7570,14 +7570,10 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
|
|
|
struct drm_device *dev = crtc->base.dev;
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
u32 dpll;
|
|
|
- bool is_sdvo;
|
|
|
struct dpll *clock = &crtc_state->dpll;
|
|
|
|
|
|
i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
|
|
|
|
|
|
- is_sdvo = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
|
|
|
- intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
|
|
|
-
|
|
|
dpll = DPLL_VGA_MODE_DIS;
|
|
|
|
|
|
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
|
|
@@ -7590,7 +7586,8 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
|
|
|
<< SDVO_MULTIPLIER_SHIFT_HIRES;
|
|
|
}
|
|
|
|
|
|
- if (is_sdvo)
|
|
|
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
|
|
|
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
|
|
dpll |= DPLL_SDVO_HIGH_SPEED;
|
|
|
|
|
|
if (crtc_state->has_dp_encoder)
|
|
@@ -8897,36 +8894,12 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
|
|
|
struct drm_crtc *crtc = &intel_crtc->base;
|
|
|
struct drm_device *dev = crtc->dev;
|
|
|
struct drm_i915_private *dev_priv = to_i915(dev);
|
|
|
- struct drm_atomic_state *state = crtc_state->base.state;
|
|
|
- struct drm_connector *connector;
|
|
|
- struct drm_connector_state *connector_state;
|
|
|
- struct intel_encoder *encoder;
|
|
|
u32 dpll, fp, fp2;
|
|
|
- int factor, i;
|
|
|
- bool is_lvds = false, is_sdvo = false;
|
|
|
-
|
|
|
- for_each_connector_in_state(state, connector, connector_state, i) {
|
|
|
- if (connector_state->crtc != crtc_state->base.crtc)
|
|
|
- continue;
|
|
|
-
|
|
|
- encoder = to_intel_encoder(connector_state->best_encoder);
|
|
|
-
|
|
|
- switch (encoder->type) {
|
|
|
- case INTEL_OUTPUT_LVDS:
|
|
|
- is_lvds = true;
|
|
|
- break;
|
|
|
- case INTEL_OUTPUT_SDVO:
|
|
|
- case INTEL_OUTPUT_HDMI:
|
|
|
- is_sdvo = true;
|
|
|
- break;
|
|
|
- default:
|
|
|
- break;
|
|
|
- }
|
|
|
- }
|
|
|
+ int factor;
|
|
|
|
|
|
/* Enable autotuning of the PLL clock (if permissible) */
|
|
|
factor = 21;
|
|
|
- if (is_lvds) {
|
|
|
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
|
|
|
if ((intel_panel_use_ssc(dev_priv) &&
|
|
|
dev_priv->vbt.lvds_ssc_freq == 100000) ||
|
|
|
(HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
|
|
@@ -8950,7 +8923,7 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
|
|
|
|
|
|
dpll = 0;
|
|
|
|
|
|
- if (is_lvds)
|
|
|
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
|
|
|
dpll |= DPLLB_MODE_LVDS;
|
|
|
else
|
|
|
dpll |= DPLLB_MODE_DAC_SERIAL;
|
|
@@ -8958,8 +8931,10 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
|
|
|
dpll |= (crtc_state->pixel_multiplier - 1)
|
|
|
<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
|
|
|
|
|
|
- if (is_sdvo)
|
|
|
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
|
|
|
+ intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
|
|
|
dpll |= DPLL_SDVO_HIGH_SPEED;
|
|
|
+
|
|
|
if (crtc_state->has_dp_encoder)
|
|
|
dpll |= DPLL_SDVO_HIGH_SPEED;
|
|
|
|
|
@@ -8983,7 +8958,8 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
- if (is_lvds && intel_panel_use_ssc(dev_priv))
|
|
|
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
|
|
|
+ intel_panel_use_ssc(dev_priv))
|
|
|
dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
|
|
|
else
|
|
|
dpll |= PLL_REF_INPUT_DREFCLK;
|