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@@ -56,7 +56,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder,
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* for MST we always configure max link bw - the spec doesn't
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* seem to suggest we should do otherwise.
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*/
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- lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
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+ lane_count = intel_dp_max_lane_count(intel_dp);
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pipe_config->lane_count = lane_count;
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@@ -343,7 +343,7 @@ intel_dp_mst_mode_valid(struct drm_connector *connector,
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int max_rate, mode_rate, max_lanes, max_link_clock;
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max_link_clock = intel_dp_max_link_rate(intel_dp);
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- max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
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+ max_lanes = intel_dp_max_lane_count(intel_dp);
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max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
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mode_rate = intel_dp_link_required(mode->clock, bpp);
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