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@@ -716,6 +716,12 @@ static const char * const energy_perf_strings[] = {
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"power",
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NULL
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};
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+static const unsigned int epp_values[] = {
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+ HWP_EPP_PERFORMANCE,
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+ HWP_EPP_BALANCE_PERFORMANCE,
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+ HWP_EPP_BALANCE_POWERSAVE,
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+ HWP_EPP_POWERSAVE
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+};
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static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
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{
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@@ -727,17 +733,14 @@ static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
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return epp;
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if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
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- /*
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- * Range:
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- * 0x00-0x3F : Performance
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- * 0x40-0x7F : Balance performance
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- * 0x80-0xBF : Balance power
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- * 0xC0-0xFF : Power
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- * The EPP is a 8 bit value, but our ranges restrict the
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- * value which can be set. Here only using top two bits
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- * effectively.
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- */
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- index = (epp >> 6) + 1;
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+ if (epp == HWP_EPP_PERFORMANCE)
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+ return 1;
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+ if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
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+ return 2;
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+ if (epp <= HWP_EPP_BALANCE_POWERSAVE)
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+ return 3;
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+ else
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+ return 4;
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} else if (static_cpu_has(X86_FEATURE_EPB)) {
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/*
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* Range:
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@@ -775,15 +778,8 @@ static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
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value &= ~GENMASK_ULL(31, 24);
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- /*
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- * If epp is not default, convert from index into
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- * energy_perf_strings to epp value, by shifting 6
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- * bits left to use only top two bits in epp.
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- * The resultant epp need to shifted by 24 bits to
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- * epp position in MSR_HWP_REQUEST.
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- */
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if (epp == -EINVAL)
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- epp = (pref_index - 1) << 6;
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+ epp = epp_values[pref_index - 1];
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value |= (u64)epp << 24;
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ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
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