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@@ -84,7 +84,15 @@ enum mx35_clks {
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static struct clk *clk[clk_max];
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-int __init mx35_clocks_init(void)
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+static struct clk ** const uart_clks[] __initconst = {
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+ &clk[ipg],
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+ &clk[uart1_gate],
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+ &clk[uart2_gate],
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+ &clk[uart3_gate],
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+ NULL
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+};
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+
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+static void __init _mx35_clocks_init(void)
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{
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void __iomem *base;
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u32 pdr0, consumer_sel, hsp_sel;
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@@ -220,6 +228,32 @@ int __init mx35_clocks_init(void)
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imx_check_clocks(clk, ARRAY_SIZE(clk));
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+ clk_prepare_enable(clk[spba_gate]);
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+ clk_prepare_enable(clk[gpio1_gate]);
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+ clk_prepare_enable(clk[gpio2_gate]);
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+ clk_prepare_enable(clk[gpio3_gate]);
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+ clk_prepare_enable(clk[iim_gate]);
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+ clk_prepare_enable(clk[emi_gate]);
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+ clk_prepare_enable(clk[max_gate]);
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+ clk_prepare_enable(clk[iomuxc_gate]);
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+
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+ /*
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+ * SCC is needed to boot via mmc after a watchdog reset. The clock code
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+ * before conversion to common clk also enabled UART1 (which isn't
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+ * handled here and not needed for mmc) and IIM (which is enabled
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+ * unconditionally above).
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+ */
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+ clk_prepare_enable(clk[scc_gate]);
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+
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+ imx_register_uart_clocks(uart_clks);
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+
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+ imx_print_silicon_rev("i.MX35", mx35_revision());
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+}
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+
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+int __init mx35_clocks_init(void)
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+{
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+ _mx35_clocks_init();
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+
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clk_register_clkdev(clk[pata_gate], NULL, "pata_imx");
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clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0");
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clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1");
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@@ -279,25 +313,6 @@ int __init mx35_clocks_init(void)
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clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
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clk_register_clkdev(clk[admux_gate], "audmux", NULL);
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- clk_prepare_enable(clk[spba_gate]);
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- clk_prepare_enable(clk[gpio1_gate]);
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- clk_prepare_enable(clk[gpio2_gate]);
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- clk_prepare_enable(clk[gpio3_gate]);
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- clk_prepare_enable(clk[iim_gate]);
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- clk_prepare_enable(clk[emi_gate]);
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- clk_prepare_enable(clk[max_gate]);
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- clk_prepare_enable(clk[iomuxc_gate]);
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-
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- /*
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- * SCC is needed to boot via mmc after a watchdog reset. The clock code
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- * before conversion to common clk also enabled UART1 (which isn't
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- * handled here and not needed for mmc) and IIM (which is enabled
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- * unconditionally above).
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- */
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- clk_prepare_enable(clk[scc_gate]);
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-
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- imx_print_silicon_rev("i.MX35", mx35_revision());
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-
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mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT, GPT_TYPE_IMX31);
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return 0;
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@@ -305,10 +320,10 @@ int __init mx35_clocks_init(void)
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static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
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{
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+ _mx35_clocks_init();
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+
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clk_data.clks = clk;
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clk_data.clk_num = ARRAY_SIZE(clk);
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of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
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-
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- mx35_clocks_init();
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}
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CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
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