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@@ -24,7 +24,7 @@
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#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
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#define MII_BCM7XXX_100TX_DISC 0x14
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#define MII_BCM7XXX_AUX_MODE 0x1d
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-#define MII_BCM7XX_64CLK_MDIO BIT(12)
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+#define MII_BCM7XXX_64CLK_MDIO BIT(12)
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#define MII_BCM7XXX_TEST 0x1f
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#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
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@@ -247,7 +247,7 @@ static int bcm7xxx_config_init(struct phy_device *phydev)
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int ret;
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/* Enable 64 clock MDIO */
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- phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
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+ phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XXX_64CLK_MDIO);
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phy_read(phydev, MII_BCM7XXX_AUX_MODE);
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/* Workaround only required for 100Mbits/sec capable PHYs */
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