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@@ -337,7 +337,7 @@ static int meson_mmc_clk_init(struct meson_host *host)
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int i, ret = 0;
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const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
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const char *clk_div_parents[1];
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- u32 clk_reg, cfg;
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+ u32 clk_reg;
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/* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
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clk_reg = 0;
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@@ -402,12 +402,6 @@ static int meson_mmc_clk_init(struct meson_host *host)
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if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk)))
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return PTR_ERR(host->cfg_div_clk);
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- /* Ensure clock starts in "auto" mode, not "always on" */
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- cfg = readl(host->regs + SD_EMMC_CFG);
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- cfg &= ~CFG_CLK_ALWAYS_ON;
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- cfg |= CFG_AUTO_CLK;
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- writel(cfg, host->regs + SD_EMMC_CFG);
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-
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ret = clk_prepare_enable(host->cfg_div_clk);
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if (ret)
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return ret;
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@@ -956,6 +950,9 @@ static int meson_mmc_probe(struct platform_device *pdev)
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if (ret)
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goto err_core_clk;
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+ /* set config to sane default */
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+ meson_mmc_cfg_init(host);
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+
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/* Stop execution */
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writel(0, host->regs + SD_EMMC_START);
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@@ -964,9 +961,6 @@ static int meson_mmc_probe(struct platform_device *pdev)
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writel(IRQ_EN_MASK, host->regs + SD_EMMC_STATUS);
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writel(IRQ_EN_MASK, host->regs + SD_EMMC_IRQ_EN);
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- /* set config to sane default */
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- meson_mmc_cfg_init(host);
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-
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ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq,
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meson_mmc_irq_thread, IRQF_SHARED,
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NULL, host);
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