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@@ -919,6 +919,82 @@ static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
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return 0;
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}
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+static int fsmc_nand_attach_chip(struct nand_chip *nand)
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+{
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+ struct mtd_info *mtd = nand_to_mtd(nand);
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+ struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
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+
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+ if (AMBA_REV_BITS(host->pid) >= 8) {
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+ switch (mtd->oobsize) {
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+ case 16:
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+ case 64:
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+ case 128:
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+ case 224:
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+ case 256:
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+ break;
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+ default:
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+ dev_warn(host->dev,
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+ "No oob scheme defined for oobsize %d\n",
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+ mtd->oobsize);
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+ return -EINVAL;
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+ }
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+
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+ mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
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+
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+ return 0;
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+ }
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+
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+ switch (nand->ecc.mode) {
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+ case NAND_ECC_HW:
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+ dev_info(host->dev, "Using 1-bit HW ECC scheme\n");
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+ nand->ecc.calculate = fsmc_read_hwecc_ecc1;
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+ nand->ecc.correct = nand_correct_data;
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+ nand->ecc.bytes = 3;
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+ nand->ecc.strength = 1;
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+ break;
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+
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+ case NAND_ECC_SOFT:
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+ if (nand->ecc.algo == NAND_ECC_BCH) {
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+ dev_info(host->dev,
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+ "Using 4-bit SW BCH ECC scheme\n");
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+ break;
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+ }
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+
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+ case NAND_ECC_ON_DIE:
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+ break;
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+
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+ default:
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+ dev_err(host->dev, "Unsupported ECC mode!\n");
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+ return -ENOTSUPP;
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+ }
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+
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+ /*
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+ * Don't set layout for BCH4 SW ECC. This will be
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+ * generated later in nand_bch_init() later.
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+ */
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+ if (nand->ecc.mode == NAND_ECC_HW) {
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+ switch (mtd->oobsize) {
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+ case 16:
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+ case 64:
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+ case 128:
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+ mtd_set_ooblayout(mtd,
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+ &fsmc_ecc1_ooblayout_ops);
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+ break;
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+ default:
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+ dev_warn(host->dev,
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+ "No oob scheme defined for oobsize %d\n",
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+ mtd->oobsize);
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+ return -EINVAL;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct nand_controller_ops fsmc_nand_controller_ops = {
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+ .attach_chip = fsmc_nand_attach_chip,
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+};
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+
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/*
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* fsmc_nand_probe - Probe function
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* @pdev: platform device structure
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@@ -1048,76 +1124,8 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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/*
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* Scan to find existence of the device
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*/
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- ret = nand_scan_ident(mtd, 1, NULL);
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- if (ret) {
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- dev_err(&pdev->dev, "No NAND Device found!\n");
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- goto release_dma_write_chan;
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- }
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-
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- if (AMBA_REV_BITS(host->pid) >= 8) {
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- switch (mtd->oobsize) {
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- case 16:
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- case 64:
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- case 128:
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- case 224:
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- case 256:
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- break;
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- default:
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- dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
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- mtd->oobsize);
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- ret = -EINVAL;
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- goto release_dma_write_chan;
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- }
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-
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- mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
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- } else {
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- switch (nand->ecc.mode) {
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- case NAND_ECC_HW:
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- dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
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- nand->ecc.calculate = fsmc_read_hwecc_ecc1;
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- nand->ecc.correct = nand_correct_data;
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- nand->ecc.bytes = 3;
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- nand->ecc.strength = 1;
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- break;
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-
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- case NAND_ECC_SOFT:
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- if (nand->ecc.algo == NAND_ECC_BCH) {
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- dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
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- break;
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- }
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-
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- case NAND_ECC_ON_DIE:
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- break;
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-
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- default:
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- dev_err(&pdev->dev, "Unsupported ECC mode!\n");
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- goto release_dma_write_chan;
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- }
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-
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- /*
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- * Don't set layout for BCH4 SW ECC. This will be
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- * generated later in nand_bch_init() later.
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- */
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- if (nand->ecc.mode == NAND_ECC_HW) {
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- switch (mtd->oobsize) {
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- case 16:
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- case 64:
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- case 128:
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- mtd_set_ooblayout(mtd,
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- &fsmc_ecc1_ooblayout_ops);
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- break;
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- default:
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- dev_warn(&pdev->dev,
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- "No oob scheme defined for oobsize %d\n",
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- mtd->oobsize);
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- ret = -EINVAL;
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- goto release_dma_write_chan;
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- }
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- }
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- }
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-
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- /* Second stage of scan to fill MTD data-structures */
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- ret = nand_scan_tail(mtd);
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+ nand->dummy_controller.ops = &fsmc_nand_controller_ops;
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+ ret = nand_scan(mtd, 1);
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if (ret)
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goto release_dma_write_chan;
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