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cirrusfb: fix 16bpp modes

The 16bpp mode did not work on the Cirrus cards as the visual type was set
to DIRECTCOLOR instead of TRUECOLOR.  The Alpine family used one incorrect
register setting so this 16bpp modes generated wrong horizontal frequency.

Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Krzysztof Helt 17 年之前
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3b921832d4
共有 1 個文件被更改,包括 2 次插入5 次删除
  1. 2 5
      drivers/video/cirrusfb.c

+ 2 - 5
drivers/video/cirrusfb.c

@@ -657,7 +657,7 @@ static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
 	case 16:
 	case 16:
 	case 32:
 	case 32:
 		info->fix.line_length = var->xres_virtual * maxclockidx;
 		info->fix.line_length = var->xres_virtual * maxclockidx;
-		info->fix.visual = FB_VISUAL_DIRECTCOLOR;
+		info->fix.visual = FB_VISUAL_TRUECOLOR;
 		break;
 		break;
 
 
 	default:
 	default:
@@ -1178,10 +1178,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
 
 
 		case BT_ALPINE:
 		case BT_ALPINE:
 			DPRINTK(" (for GD543x)\n");
 			DPRINTK(" (for GD543x)\n");
-			if (var->xres >= 1024)
-				vga_wseq(regbase, CL_SEQR7, 0xa7);
-			else
-				vga_wseq(regbase, CL_SEQR7, 0xa3);
+			vga_wseq(regbase, CL_SEQR7, 0xa7);
 			cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
 			cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
 			break;
 			break;