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@@ -51,15 +51,9 @@ struct cls_uart_struct {
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#define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
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-#define UART_16654_FCR_TXTRIGGER_8 0x0
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#define UART_16654_FCR_TXTRIGGER_16 0x10
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-#define UART_16654_FCR_TXTRIGGER_32 0x20
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-#define UART_16654_FCR_TXTRIGGER_56 0x30
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-
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-#define UART_16654_FCR_RXTRIGGER_8 0x0
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#define UART_16654_FCR_RXTRIGGER_16 0x40
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#define UART_16654_FCR_RXTRIGGER_56 0x80
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-#define UART_16654_FCR_RXTRIGGER_60 0xC0
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/* Received CTS/RTS change of state */
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#define UART_IIR_CTSRTS 0x20
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@@ -76,13 +70,6 @@ struct cls_uart_struct {
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#define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
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#define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
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#define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
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-
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-/* Indicates whether chip saw an incoming XOFF char */
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-#define UART_EXAR654_XOFF_DETECT 0x1
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-
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-/* Indicates whether chip saw an incoming XON char */
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-#define UART_EXAR654_XON_DETECT 0x2
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-
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#define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
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#define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
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#define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
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