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@@ -324,6 +324,26 @@ static void radix_init_amor(void)
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mtspr(SPRN_AMOR, (3ul << 62));
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}
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+static void radix_init_iamr(void)
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+{
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+ unsigned long iamr;
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+
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+ /*
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+ * The IAMR should set to 0 on DD1.
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+ */
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+ if (cpu_has_feature(CPU_FTR_POWER9_DD1))
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+ iamr = 0;
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+ else
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+ iamr = (1ul << 62);
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+
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+ /*
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+ * Radix always uses key0 of the IAMR to determine if an access is
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+ * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
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+ * fetch.
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+ */
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+ mtspr(SPRN_IAMR, iamr);
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+}
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+
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void __init radix__early_init_mmu(void)
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{
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unsigned long lpcr;
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@@ -385,6 +405,7 @@ void __init radix__early_init_mmu(void)
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memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
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+ radix_init_iamr();
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radix_init_pgtable();
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}
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@@ -402,6 +423,7 @@ void radix__early_init_mmu_secondary(void)
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__pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
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radix_init_amor();
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}
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+ radix_init_iamr();
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}
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void radix__mmu_cleanup_all(void)
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