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@@ -23,6 +23,185 @@
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*/
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#include "priv.h"
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+static int
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+gk104_pcie_version_supported(struct nvkm_pci *pci)
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+{
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+ return (nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x4) == 0x4 ? 2 : 1;
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+}
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+
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+static void
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+gk104_pcie_set_cap_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed)
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+{
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+ struct nvkm_device *device = pci->subdev.device;
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+
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+ switch (speed) {
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+ case NVKM_PCIE_SPEED_2_5:
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+ gf100_pcie_set_cap_speed(pci, false);
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+ nvkm_mask(device, 0x8c1c0, 0x30000, 0x10000);
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+ break;
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+ case NVKM_PCIE_SPEED_5_0:
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+ gf100_pcie_set_cap_speed(pci, true);
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+ nvkm_mask(device, 0x8c1c0, 0x30000, 0x20000);
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+ break;
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+ case NVKM_PCIE_SPEED_8_0:
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+ gf100_pcie_set_cap_speed(pci, true);
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+ nvkm_mask(device, 0x8c1c0, 0x30000, 0x30000);
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+ break;
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+ }
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+}
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+
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+static enum nvkm_pcie_speed
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+gk104_pcie_cap_speed(struct nvkm_pci *pci)
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+{
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+ int speed = gf100_pcie_cap_speed(pci);
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+
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+ if (speed == 0)
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+ return NVKM_PCIE_SPEED_2_5;
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+
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+ if (speed >= 1) {
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+ int speed2 = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x30000;
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+ switch (speed2) {
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+ case 0x00000:
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+ case 0x10000:
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+ return NVKM_PCIE_SPEED_2_5;
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+ case 0x20000:
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+ return NVKM_PCIE_SPEED_5_0;
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+ case 0x30000:
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+ return NVKM_PCIE_SPEED_8_0;
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+ }
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+ }
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+
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+ return -EINVAL;
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+}
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+
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+static void
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+gk104_pcie_set_lnkctl_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed)
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+{
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+ u8 reg_v = 0;
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+ switch (speed) {
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+ case NVKM_PCIE_SPEED_2_5:
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+ reg_v = 1;
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+ break;
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+ case NVKM_PCIE_SPEED_5_0:
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+ reg_v = 2;
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+ break;
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+ case NVKM_PCIE_SPEED_8_0:
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+ reg_v = 3;
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+ break;
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+ }
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+ nvkm_pci_mask(pci, 0xa8, 0x3, reg_v);
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+}
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+
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+static enum nvkm_pcie_speed
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+gk104_pcie_lnkctl_speed(struct nvkm_pci *pci)
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+{
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+ u8 reg_v = nvkm_pci_rd32(pci, 0xa8) & 0x3;
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+ switch (reg_v) {
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+ case 0:
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+ case 1:
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+ return NVKM_PCIE_SPEED_2_5;
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+ case 2:
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+ return NVKM_PCIE_SPEED_5_0;
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+ case 3:
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+ return NVKM_PCIE_SPEED_8_0;
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+ }
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+ return -1;
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+}
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+
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+static enum nvkm_pcie_speed
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+gk104_pcie_max_speed(struct nvkm_pci *pci)
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+{
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+ u32 max_speed = nvkm_rd32(pci->subdev.device, 0x8c1c0) & 0x300000;
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+ switch (max_speed) {
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+ case 0x000000:
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+ return NVKM_PCIE_SPEED_8_0;
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+ case 0x100000:
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+ return NVKM_PCIE_SPEED_5_0;
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+ case 0x200000:
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+ return NVKM_PCIE_SPEED_2_5;
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+ }
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+ return NVKM_PCIE_SPEED_2_5;
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+}
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+
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+static void
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+gk104_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed)
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+{
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+ struct nvkm_device *device = pci->subdev.device;
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+ u32 mask_value;
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+
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+ switch (speed) {
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+ case NVKM_PCIE_SPEED_8_0:
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+ mask_value = 0x00000;
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+ break;
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+ case NVKM_PCIE_SPEED_5_0:
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+ mask_value = 0x40000;
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+ break;
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+ case NVKM_PCIE_SPEED_2_5:
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+ default:
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+ mask_value = 0x80000;
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+ break;
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+ }
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+
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+ nvkm_mask(device, 0x8c040, 0xc0000, mask_value);
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+ nvkm_mask(device, 0x8c040, 0x1, 0x1);
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+}
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+
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+static int
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+gk104_pcie_init(struct nvkm_pci * pci)
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+{
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+ enum nvkm_pcie_speed lnkctl_speed, max_speed, cap_speed;
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+ struct nvkm_subdev *subdev = &pci->subdev;
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+
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+ if (gf100_pcie_version(pci) < 2)
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+ return 0;
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+
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+ lnkctl_speed = gk104_pcie_lnkctl_speed(pci);
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+ max_speed = gk104_pcie_max_speed(pci);
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+ cap_speed = gk104_pcie_cap_speed(pci);
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+
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+ if (cap_speed != max_speed) {
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+ nvkm_trace(subdev, "adjusting cap to max speed\n");
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+ gk104_pcie_set_cap_speed(pci, max_speed);
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+ cap_speed = gk104_pcie_cap_speed(pci);
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+ if (cap_speed != max_speed)
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+ nvkm_warn(subdev, "failed to adjust cap speed\n");
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+ }
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+
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+ if (lnkctl_speed != max_speed) {
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+ nvkm_debug(subdev, "adjusting lnkctl to max speed\n");
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+ gk104_pcie_set_lnkctl_speed(pci, max_speed);
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+ lnkctl_speed = gk104_pcie_lnkctl_speed(pci);
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+ if (lnkctl_speed != max_speed)
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+ nvkm_error(subdev, "failed to adjust lnkctl speed\n");
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+ }
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+
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+ return 0;
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+}
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+
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+static int
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+gk104_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width)
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+{
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+ struct nvkm_subdev *subdev = &pci->subdev;
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+ enum nvkm_pcie_speed lnk_ctl_speed = gk104_pcie_lnkctl_speed(pci);
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+ enum nvkm_pcie_speed lnk_cap_speed = gk104_pcie_cap_speed(pci);
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+
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+ if (speed > lnk_cap_speed) {
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+ speed = lnk_cap_speed;
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+ nvkm_warn(subdev, "dropping requested speed due too low cap"
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+ " speed\n");
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+ }
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+
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+ if (speed > lnk_ctl_speed) {
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+ speed = lnk_ctl_speed;
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+ nvkm_warn(subdev, "dropping requested speed due too low"
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+ " lnkctl speed\n");
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+ }
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+
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+ gk104_pcie_set_link_speed(pci, speed);
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+ return 0;
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+}
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+
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+
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static const struct nvkm_pci_func
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gk104_pci_func = {
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.init = g84_pci_init,
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@@ -30,6 +209,16 @@ gk104_pci_func = {
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.wr08 = nv40_pci_wr08,
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.wr32 = nv40_pci_wr32,
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.msi_rearm = nv40_pci_msi_rearm,
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+
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+ .pcie.init = gk104_pcie_init,
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+ .pcie.set_link = gk104_pcie_set_link,
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+
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+ .pcie.max_speed = gk104_pcie_max_speed,
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+ .pcie.cur_speed = g84_pcie_cur_speed,
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+
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+ .pcie.set_version = gf100_pcie_set_version,
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+ .pcie.version = gf100_pcie_version,
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+ .pcie.version_supported = gk104_pcie_version_supported,
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};
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int
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