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@@ -71,6 +71,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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};
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/* irqpin1: IRQ8 - IRQ15 */
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@@ -91,6 +92,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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};
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/* irqpin2: IRQ16 - IRQ23 */
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@@ -111,6 +113,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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};
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/* irqpin3: IRQ24 - IRQ31 */
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@@ -131,6 +134,7 @@
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH
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0 149 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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};
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ether: ethernet@e9a00000 {
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@@ -448,8 +452,8 @@
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xe6150138 4>, <0xe6150040 4>;
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- clocks = <&sub_clk>, <&sub_clk>,
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- <&cpg_clocks R8A7740_CLK_HP>,
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+ clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
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+ <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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<&cpg_clocks R8A7740_CLK_HP>,
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@@ -458,7 +462,8 @@
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<&sub_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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- R8A7740_CLK_SCIFA6 R8A7740_CLK_SCIFA7
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+ R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA
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+ R8A7740_CLK_SCIFA7
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R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2
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R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC
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R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB
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@@ -467,7 +472,8 @@
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R8A7740_CLK_SCIFA4
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>;
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clock-output-names =
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- "scifa6", "scifa7", "dmac1", "dmac2", "dmac3",
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+ "scifa6", "intca",
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+ "scifa7", "dmac1", "dmac2", "dmac3",
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"usbdmac", "scifa5", "scifb", "scifa0", "scifa1",
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"scifa2", "scifa3", "scifa4";
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};
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