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@@ -84,7 +84,7 @@ static const struct dce110_timing_generator_offsets reg_offsets[] = {
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#define DCP_REG(reg) (reg + tg110->offsets.dcp)
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#define DMIF_REG(reg) (reg + tg110->offsets.dmif)
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-void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
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+static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_khz)
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{
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uint64_t pix_dur;
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uint32_t addr = mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1
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@@ -115,6 +115,68 @@ static void program_timing(struct timing_generator *tg,
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dce110_tg_program_timing(tg, timing, use_vbios);
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}
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+static void dce80_timing_generator_enable_advanced_request(
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+ struct timing_generator *tg,
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+ bool enable,
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+ const struct dc_crtc_timing *timing)
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+{
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+ struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
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+ uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
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+ uint32_t value = dm_read_reg(tg->ctx, addr);
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+
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+ if (enable) {
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+ set_reg_field_value(
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+ value,
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+ 0,
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+ CRTC_START_LINE_CONTROL,
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+ CRTC_LEGACY_REQUESTOR_EN);
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+ } else {
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+ set_reg_field_value(
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+ value,
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+ 1,
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+ CRTC_START_LINE_CONTROL,
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+ CRTC_LEGACY_REQUESTOR_EN);
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+ }
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+
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+ if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
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+ set_reg_field_value(
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+ value,
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+ 3,
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+ CRTC_START_LINE_CONTROL,
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+ CRTC_ADVANCED_START_LINE_POSITION);
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+ set_reg_field_value(
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+ value,
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+ 0,
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+ CRTC_START_LINE_CONTROL,
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+ CRTC_PREFETCH_EN);
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+ } else {
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+ set_reg_field_value(
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+ value,
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+ 4,
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+ CRTC_START_LINE_CONTROL,
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+ CRTC_ADVANCED_START_LINE_POSITION);
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+ set_reg_field_value(
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+ value,
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+ 1,
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+ CRTC_START_LINE_CONTROL,
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+ CRTC_PREFETCH_EN);
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+ }
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+
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+ set_reg_field_value(
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+ value,
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+ 1,
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+ CRTC_START_LINE_CONTROL,
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+ CRTC_PROGRESSIVE_START_LINE_EARLY);
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+
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+ set_reg_field_value(
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+ value,
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+ 1,
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+ CRTC_START_LINE_CONTROL,
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+ CRTC_INTERLACE_START_LINE_EARLY);
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+
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+ dm_write_reg(tg->ctx, addr, value);
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+}
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+
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static const struct timing_generator_funcs dce80_tg_funcs = {
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.validate_timing = dce110_tg_validate_timing,
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.program_timing = program_timing,
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@@ -176,64 +238,3 @@ void dce80_timing_generator_construct(
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tg110->min_h_back_porch = 4;
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}
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-void dce80_timing_generator_enable_advanced_request(
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- struct timing_generator *tg,
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- bool enable,
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- const struct dc_crtc_timing *timing)
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-{
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- struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
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- uint32_t addr = CRTC_REG(mmCRTC_START_LINE_CONTROL);
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- uint32_t value = dm_read_reg(tg->ctx, addr);
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-
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- if (enable) {
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- set_reg_field_value(
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- value,
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- 0,
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- CRTC_START_LINE_CONTROL,
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- CRTC_LEGACY_REQUESTOR_EN);
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- } else {
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- set_reg_field_value(
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- value,
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- 1,
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- CRTC_START_LINE_CONTROL,
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- CRTC_LEGACY_REQUESTOR_EN);
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- }
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-
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- if ((timing->v_sync_width + timing->v_front_porch) <= 3) {
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- set_reg_field_value(
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- value,
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- 3,
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- CRTC_START_LINE_CONTROL,
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- CRTC_ADVANCED_START_LINE_POSITION);
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- set_reg_field_value(
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- value,
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- 0,
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- CRTC_START_LINE_CONTROL,
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- CRTC_PREFETCH_EN);
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- } else {
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- set_reg_field_value(
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- value,
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- 4,
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- CRTC_START_LINE_CONTROL,
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- CRTC_ADVANCED_START_LINE_POSITION);
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- set_reg_field_value(
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- value,
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- 1,
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- CRTC_START_LINE_CONTROL,
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- CRTC_PREFETCH_EN);
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- }
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-
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- set_reg_field_value(
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- value,
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- 1,
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- CRTC_START_LINE_CONTROL,
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- CRTC_PROGRESSIVE_START_LINE_EARLY);
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-
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- set_reg_field_value(
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- value,
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- 1,
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- CRTC_START_LINE_CONTROL,
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- CRTC_INTERLACE_START_LINE_EARLY);
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-
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- dm_write_reg(tg->ctx, addr, value);
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-}
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