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@@ -103,7 +103,10 @@
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#size-cells = <1>;
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assigned-clocks = <&clk_s_d2_quadfs 0>,
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- <&clk_s_d2_quadfs 0>,
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+ <&clk_s_d2_quadfs 1>,
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+ <&clk_s_c0_pll1 0>,
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+ <&clk_s_c0_flexgen CLK_COMPO_DVP>,
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+ <&clk_s_c0_flexgen CLK_MAIN_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
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<&clk_s_d2_flexgen CLK_PIX_GDP1>,
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@@ -113,14 +116,21 @@
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assigned-clock-parents = <0>,
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<0>,
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+ <0>,
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+ <&clk_s_c0_pll1 0>,
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+ <&clk_s_c0_pll1 0>,
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<&clk_s_d2_quadfs 0>,
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- <&clk_s_d2_quadfs 0>,
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+ <&clk_s_d2_quadfs 1>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 0>;
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- assigned-clock-rates = <297000000>, <297000000>;
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+ assigned-clock-rates = <297000000>,
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+ <108000000>,
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+ <0>,
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+ <400000000>,
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+ <400000000>;
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ranges;
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