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@@ -820,6 +820,7 @@ struct dwc2_dma_desc {
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#define HOST_DMA_ISOC_NBYTES_SHIFT 0
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#define HOST_DMA_ISOC_NBYTES_SHIFT 0
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#define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
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#define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
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#define HOST_DMA_NBYTES_SHIFT 0
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#define HOST_DMA_NBYTES_SHIFT 0
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+#define HOST_DMA_NBYTES_LIMIT 131071
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/* Device Mode DMA descriptor status quadlet */
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/* Device Mode DMA descriptor status quadlet */
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@@ -856,7 +857,6 @@ struct dwc2_dma_desc {
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#define DEV_DMA_NBYTES_SHIFT 0
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#define DEV_DMA_NBYTES_SHIFT 0
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#define DEV_DMA_NBYTES_LIMIT 0xffff
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#define DEV_DMA_NBYTES_LIMIT 0xffff
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-#define MAX_DMA_DESC_SIZE 131071
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#define MAX_DMA_DESC_NUM_GENERIC 64
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#define MAX_DMA_DESC_NUM_GENERIC 64
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#define MAX_DMA_DESC_NUM_HS_ISOC 256
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#define MAX_DMA_DESC_NUM_HS_ISOC 256
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