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@@ -18,22 +18,29 @@
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#define pr_fmt(fmt) "mvebu-pmsu: " fmt
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+#include <linux/clk.h>
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#include <linux/cpu_pm.h>
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-#include <linux/kernel.h>
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+#include <linux/delay.h>
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#include <linux/init.h>
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-#include <linux/of_address.h>
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#include <linux/io.h>
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+#include <linux/kernel.h>
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+#include <linux/mbus.h>
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+#include <linux/of_address.h>
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+#include <linux/of_device.h>
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#include <linux/platform_device.h>
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-#include <linux/smp.h>
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+#include <linux/pm_opp.h>
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#include <linux/resource.h>
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+#include <linux/slab.h>
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+#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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+#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#include <asm/tlbflush.h>
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#include "common.h"
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+#include "armada-370-xp.h"
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-static void __iomem *pmsu_mp_base;
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#define PMSU_BASE_OFFSET 0x100
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#define PMSU_REG_SIZE 0x1000
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@@ -57,20 +64,45 @@ static void __iomem *pmsu_mp_base;
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#define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
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#define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
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+#define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
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+#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1)
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+#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17)
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+
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#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
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/* PMSU fabric registers */
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#define L2C_NFABRIC_PM_CTL 0x4
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#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
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+/* PMSU delay registers */
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+#define PMSU_POWERDOWN_DELAY 0xF04
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+#define PMSU_POWERDOWN_DELAY_PMU BIT(1)
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+#define PMSU_POWERDOWN_DELAY_MASK 0xFFFE
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+#define PMSU_DFLT_ARMADA38X_DELAY 0x64
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+
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+/* CA9 MPcore SoC Control registers */
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+
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+#define MPCORE_RESET_CTL 0x64
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+#define MPCORE_RESET_CTL_L2 BIT(0)
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+#define MPCORE_RESET_CTL_DEBUG BIT(16)
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+
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+#define SRAM_PHYS_BASE 0xFFFF0000
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+#define BOOTROM_BASE 0xFFF00000
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+#define BOOTROM_SIZE 0x100000
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+
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+#define ARMADA_370_CRYPT0_ENG_TARGET 0x9
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+#define ARMADA_370_CRYPT0_ENG_ATTR 0x1
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+
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extern void ll_disable_coherency(void);
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extern void ll_enable_coherency(void);
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extern void armada_370_xp_cpu_resume(void);
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+extern void armada_38x_cpu_resume(void);
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-static struct platform_device armada_xp_cpuidle_device = {
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- .name = "cpuidle-armada-370-xp",
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-};
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+static phys_addr_t pmsu_mp_phys_base;
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+static void __iomem *pmsu_mp_base;
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+
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+static void *mvebu_cpu_resume;
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static struct of_device_id of_pmsu_table[] = {
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{ .compatible = "marvell,armada-370-pmsu", },
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@@ -85,7 +117,49 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
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PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
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}
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-static int __init armada_370_xp_pmsu_init(void)
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+extern unsigned char mvebu_boot_wa_start;
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+extern unsigned char mvebu_boot_wa_end;
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+
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+/*
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+ * This function sets up the boot address workaround needed for SMP
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+ * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
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+ * BootROM Mbus window, and instead remaps a crypto SRAM into which a
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+ * custom piece of code is copied to replace the problematic BootROM.
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+ */
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+int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
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+ unsigned int crypto_eng_attribute,
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+ phys_addr_t resume_addr_reg)
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+{
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+ void __iomem *sram_virt_base;
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+ u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;
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+
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+ mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
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+ mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
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+ SRAM_PHYS_BASE, SZ_64K);
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+
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+ sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
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+ if (!sram_virt_base) {
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+ pr_err("Unable to map SRAM to setup the boot address WA\n");
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+ return -ENOMEM;
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+ }
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+
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+ memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
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+
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+ /*
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+ * The last word of the code copied in SRAM must contain the
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+ * physical base address of the PMSU register. We
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+ * intentionally store this address in the native endianness
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+ * of the system.
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+ */
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+ __raw_writel((unsigned long)resume_addr_reg,
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+ sram_virt_base + code_len - 4);
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+
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+ iounmap(sram_virt_base);
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+
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+ return 0;
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+}
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+
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+static int __init mvebu_v7_pmsu_init(void)
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{
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struct device_node *np;
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struct resource res;
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@@ -116,6 +190,8 @@ static int __init armada_370_xp_pmsu_init(void)
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goto out;
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}
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+ pmsu_mp_phys_base = res.start;
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+
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pmsu_mp_base = ioremap(res.start, resource_size(&res));
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if (!pmsu_mp_base) {
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pr_err("unable to map registers\n");
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@@ -129,7 +205,7 @@ static int __init armada_370_xp_pmsu_init(void)
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return ret;
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}
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-static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
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+static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
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{
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u32 reg;
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@@ -142,8 +218,14 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
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writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
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}
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+enum pmsu_idle_prepare_flags {
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+ PMSU_PREPARE_NORMAL = 0,
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+ PMSU_PREPARE_DEEP_IDLE = BIT(0),
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+ PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
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+};
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+
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/* No locking is needed because we only access per-CPU registers */
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-int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
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+static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
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{
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unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
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u32 reg;
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@@ -167,17 +249,34 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
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reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
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/* ask HW to power down the L2 Cache if needed */
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- if (deepidle)
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+ if (flags & PMSU_PREPARE_DEEP_IDLE)
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reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
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/* request power down */
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reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
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writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
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- /* Disable snoop disable by HW - SW is taking care of it */
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- reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
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- reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
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- writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
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+ if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
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+ /* Disable snoop disable by HW - SW is taking care of it */
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+ reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
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+ reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
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+ writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
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+ }
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+
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+ return 0;
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+}
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+
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+int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
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+{
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+ unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
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+ int ret;
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+
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+ if (deepidle)
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+ flags |= PMSU_PREPARE_DEEP_IDLE;
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+
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+ ret = mvebu_v7_pmsu_idle_prepare(flags);
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+ if (ret)
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+ return ret;
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v7_exit_coherency_flush(all);
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@@ -203,7 +302,7 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
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"isb "
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: : : "r0");
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- pr_warn("Failed to suspend the system\n");
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+ pr_debug("Failed to suspend the system\n");
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return 0;
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}
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@@ -213,15 +312,40 @@ static int armada_370_xp_cpu_suspend(unsigned long deepidle)
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return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
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}
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+static int armada_38x_do_cpu_suspend(unsigned long deepidle)
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+{
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+ unsigned long flags = 0;
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+
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+ if (deepidle)
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+ flags |= PMSU_PREPARE_DEEP_IDLE;
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+
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+ mvebu_v7_pmsu_idle_prepare(flags);
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+ /*
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+ * Already flushed cache, but do it again as the outer cache
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+ * functions dirty the cache with spinlocks
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+ */
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+ v7_exit_coherency_flush(louis);
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+
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+ scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
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+
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+ cpu_do_idle();
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+
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+ return 1;
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+}
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+
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+static int armada_38x_cpu_suspend(unsigned long deepidle)
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+{
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+ return cpu_suspend(false, armada_38x_do_cpu_suspend);
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+}
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+
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/* No locking is needed because we only access per-CPU registers */
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-void armada_370_xp_pmsu_idle_exit(void)
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+void mvebu_v7_pmsu_idle_exit(void)
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{
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unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
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u32 reg;
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if (pmsu_mp_base == NULL)
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return;
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-
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/* cancel ask HW to power down the L2 Cache if possible */
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reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
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reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
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@@ -236,53 +360,292 @@ void armada_370_xp_pmsu_idle_exit(void)
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writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
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}
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-static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
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+static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
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unsigned long action, void *hcpu)
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{
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if (action == CPU_PM_ENTER) {
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unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
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- mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
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+ mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
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} else if (action == CPU_PM_EXIT) {
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- armada_370_xp_pmsu_idle_exit();
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+ mvebu_v7_pmsu_idle_exit();
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}
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return NOTIFY_OK;
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}
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-static struct notifier_block armada_370_xp_cpu_pm_notifier = {
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- .notifier_call = armada_370_xp_cpu_pm_notify,
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+static struct notifier_block mvebu_v7_cpu_pm_notifier = {
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+ .notifier_call = mvebu_v7_cpu_pm_notify,
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};
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-static int __init armada_370_xp_cpu_pm_init(void)
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+static struct platform_device mvebu_v7_cpuidle_device;
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+
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+static __init int armada_370_cpuidle_init(void)
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{
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struct device_node *np;
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+ phys_addr_t redirect_reg;
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+
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+ np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
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+ if (!np)
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+ return -ENODEV;
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+ of_node_put(np);
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/*
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- * Check that all the requirements are available to enable
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- * cpuidle. So far, it is only supported on Armada XP, cpuidle
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- * needs the coherency fabric and the PMSU enabled
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+ * On Armada 370, there is "a slow exit process from the deep
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+ * idle state due to heavy L1/L2 cache cleanup operations
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+ * performed by the BootROM software". To avoid this, we
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+ * replace the restart code of the bootrom by a a simple jump
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+ * to the boot address. Then the code located at this boot
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+ * address will take care of the initialization.
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*/
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+ redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
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+ mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
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+ ARMADA_370_CRYPT0_ENG_ATTR,
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+ redirect_reg);
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- if (!of_machine_is_compatible("marvell,armadaxp"))
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- return 0;
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+ mvebu_cpu_resume = armada_370_xp_cpu_resume;
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+ mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
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+ mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
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+
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+ return 0;
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+}
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+
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+static __init int armada_38x_cpuidle_init(void)
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+{
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+ struct device_node *np;
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+ void __iomem *mpsoc_base;
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+ u32 reg;
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+
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+ np = of_find_compatible_node(NULL, NULL,
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+ "marvell,armada-380-coherency-fabric");
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+ if (!np)
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+ return -ENODEV;
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+ of_node_put(np);
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+
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+ np = of_find_compatible_node(NULL, NULL,
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+ "marvell,armada-380-mpcore-soc-ctrl");
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+ if (!np)
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+ return -ENODEV;
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+ mpsoc_base = of_iomap(np, 0);
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+ BUG_ON(!mpsoc_base);
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+ of_node_put(np);
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+
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+ /* Set up reset mask when powering down the cpus */
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+ reg = readl(mpsoc_base + MPCORE_RESET_CTL);
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+ reg |= MPCORE_RESET_CTL_L2;
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+ reg |= MPCORE_RESET_CTL_DEBUG;
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+ writel(reg, mpsoc_base + MPCORE_RESET_CTL);
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+ iounmap(mpsoc_base);
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+
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+ /* Set up delay */
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+ reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
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+ reg &= ~PMSU_POWERDOWN_DELAY_MASK;
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+ reg |= PMSU_DFLT_ARMADA38X_DELAY;
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+ reg |= PMSU_POWERDOWN_DELAY_PMU;
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+ writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
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+
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+ mvebu_cpu_resume = armada_38x_cpu_resume;
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+ mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
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+ mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
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+
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+ return 0;
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+}
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+
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+static __init int armada_xp_cpuidle_init(void)
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+{
|
|
|
+ struct device_node *np;
|
|
|
|
|
|
np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
|
|
|
if (!np)
|
|
|
- return 0;
|
|
|
+ return -ENODEV;
|
|
|
of_node_put(np);
|
|
|
|
|
|
+ mvebu_cpu_resume = armada_370_xp_cpu_resume;
|
|
|
+ mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
|
|
|
+ mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int __init mvebu_v7_cpu_pm_init(void)
|
|
|
+{
|
|
|
+ struct device_node *np;
|
|
|
+ int ret;
|
|
|
+
|
|
|
np = of_find_matching_node(NULL, of_pmsu_table);
|
|
|
if (!np)
|
|
|
return 0;
|
|
|
of_node_put(np);
|
|
|
|
|
|
- armada_370_xp_pmsu_enable_l2_powerdown_onidle();
|
|
|
- armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
|
|
|
- platform_device_register(&armada_xp_cpuidle_device);
|
|
|
- cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier);
|
|
|
+ if (of_machine_is_compatible("marvell,armadaxp"))
|
|
|
+ ret = armada_xp_cpuidle_init();
|
|
|
+ else if (of_machine_is_compatible("marvell,armada370"))
|
|
|
+ ret = armada_370_cpuidle_init();
|
|
|
+ else if (of_machine_is_compatible("marvell,armada380"))
|
|
|
+ ret = armada_38x_cpuidle_init();
|
|
|
+ else
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ mvebu_v7_pmsu_enable_l2_powerdown_onidle();
|
|
|
+ platform_device_register(&mvebu_v7_cpuidle_device);
|
|
|
+ cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+arch_initcall(mvebu_v7_cpu_pm_init);
|
|
|
+early_initcall(mvebu_v7_pmsu_init);
|
|
|
+
|
|
|
+static void mvebu_pmsu_dfs_request_local(void *data)
|
|
|
+{
|
|
|
+ u32 reg;
|
|
|
+ u32 cpu = smp_processor_id();
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ local_irq_save(flags);
|
|
|
+
|
|
|
+ /* Prepare to enter idle */
|
|
|
+ reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
|
|
|
+ reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
|
|
|
+ PMSU_STATUS_AND_MASK_IRQ_MASK |
|
|
|
+ PMSU_STATUS_AND_MASK_FIQ_MASK;
|
|
|
+ writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
|
|
|
+
|
|
|
+ /* Request the DFS transition */
|
|
|
+ reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
|
|
|
+ reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
|
|
|
+ writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
|
|
|
+
|
|
|
+ /* The fact of entering idle will trigger the DFS transition */
|
|
|
+ wfi();
|
|
|
+
|
|
|
+ /*
|
|
|
+ * We're back from idle, the DFS transition has completed,
|
|
|
+ * clear the idle wait indication.
|
|
|
+ */
|
|
|
+ reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
|
|
|
+ reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
|
|
|
+ writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
|
|
|
+
|
|
|
+ local_irq_restore(flags);
|
|
|
+}
|
|
|
+
|
|
|
+int mvebu_pmsu_dfs_request(int cpu)
|
|
|
+{
|
|
|
+ unsigned long timeout;
|
|
|
+ int hwcpu = cpu_logical_map(cpu);
|
|
|
+ u32 reg;
|
|
|
+
|
|
|
+ /* Clear any previous DFS DONE event */
|
|
|
+ reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
|
|
+ reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
|
|
|
+ writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
|
|
+
|
|
|
+ /* Mask the DFS done interrupt, since we are going to poll */
|
|
|
+ reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
|
|
+ reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
|
|
|
+ writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
|
|
+
|
|
|
+ /* Trigger the DFS on the appropriate CPU */
|
|
|
+ smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
|
|
|
+ NULL, false);
|
|
|
+
|
|
|
+ /* Poll until the DFS done event is generated */
|
|
|
+ timeout = jiffies + HZ;
|
|
|
+ while (time_before(jiffies, timeout)) {
|
|
|
+ reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
|
|
+ if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
|
|
|
+ break;
|
|
|
+ udelay(10);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (time_after(jiffies, timeout))
|
|
|
+ return -ETIME;
|
|
|
+
|
|
|
+ /* Restore the DFS mask to its original state */
|
|
|
+ reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
|
|
+ reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
|
|
|
+ writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int __init armada_xp_pmsu_cpufreq_init(void)
|
|
|
+{
|
|
|
+ struct device_node *np;
|
|
|
+ struct resource res;
|
|
|
+ int ret, cpu;
|
|
|
+
|
|
|
+ if (!of_machine_is_compatible("marvell,armadaxp"))
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * In order to have proper cpufreq handling, we need to ensure
|
|
|
+ * that the Device Tree description of the CPU clock includes
|
|
|
+ * the definition of the PMU DFS registers. If not, we do not
|
|
|
+ * register the clock notifier and the cpufreq driver. This
|
|
|
+ * piece of code is only for compatibility with old Device
|
|
|
+ * Trees.
|
|
|
+ */
|
|
|
+ np = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-cpu-clock");
|
|
|
+ if (!np)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ ret = of_address_to_resource(np, 1, &res);
|
|
|
+ if (ret) {
|
|
|
+ pr_warn(FW_WARN "not enabling cpufreq, deprecated armada-xp-cpu-clock binding\n");
|
|
|
+ of_node_put(np);
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ of_node_put(np);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * For each CPU, this loop registers the operating points
|
|
|
+ * supported (which are the nominal CPU frequency and half of
|
|
|
+ * it), and registers the clock notifier that will take care
|
|
|
+ * of doing the PMSU part of a frequency transition.
|
|
|
+ */
|
|
|
+ for_each_possible_cpu(cpu) {
|
|
|
+ struct device *cpu_dev;
|
|
|
+ struct clk *clk;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ cpu_dev = get_cpu_device(cpu);
|
|
|
+ if (!cpu_dev) {
|
|
|
+ pr_err("Cannot get CPU %d\n", cpu);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ clk = clk_get(cpu_dev, 0);
|
|
|
+ if (IS_ERR(clk)) {
|
|
|
+ pr_err("Cannot get clock for CPU %d\n", cpu);
|
|
|
+ return PTR_ERR(clk);
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * In case of a failure of dev_pm_opp_add(), we don't
|
|
|
+ * bother with cleaning up the registered OPP (there's
|
|
|
+ * no function to do so), and simply cancel the
|
|
|
+ * registration of the cpufreq device.
|
|
|
+ */
|
|
|
+ ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0);
|
|
|
+ if (ret) {
|
|
|
+ clk_put(clk);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0);
|
|
|
+ if (ret) {
|
|
|
+ clk_put(clk);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
+ platform_device_register_simple("cpufreq-generic", -1, NULL, 0);
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-arch_initcall(armada_370_xp_cpu_pm_init);
|
|
|
-early_initcall(armada_370_xp_pmsu_init);
|
|
|
+device_initcall(armada_xp_pmsu_cpufreq_init);
|
Arnd Bergmann