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@@ -684,6 +684,36 @@ int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev)
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return ret;
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}
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+union gfx_info {
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+ ATOM_GFX_INFO_V2_1 info;
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+};
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+
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+int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev)
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+{
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+ struct amdgpu_mode_info *mode_info = &adev->mode_info;
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+ int index = GetIndexIntoMasterTable(DATA, GFX_Info);
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+ uint8_t frev, crev;
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+ uint16_t data_offset;
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+ int ret = -EINVAL;
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+
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+ if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
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+ &frev, &crev, &data_offset)) {
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+ union gfx_info *gfx_info = (union gfx_info *)
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+ (mode_info->atom_context->bios + data_offset);
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+
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+ adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines;
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+ adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes;
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+ adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh;
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+ adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se;
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+ adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se;
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+ adev->gfx.config.max_texture_channel_caches =
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+ gfx_info->info.max_texture_channel_caches;
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+
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+ ret = 0;
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+ }
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+ return ret;
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+}
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+
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union igp_info {
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struct _ATOM_INTEGRATED_SYSTEM_INFO info;
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struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
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