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@@ -2639,10 +2639,45 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
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struct amdgpu_device *adev = f->f_inode->i_private;
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struct amdgpu_device *adev = f->f_inode->i_private;
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ssize_t result = 0;
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ssize_t result = 0;
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int r;
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int r;
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+ bool pm_pg_lock, use_bank;
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+ unsigned instance_bank, sh_bank, se_bank;
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if (size & 0x3 || *pos & 0x3)
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if (size & 0x3 || *pos & 0x3)
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return -EINVAL;
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return -EINVAL;
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+ /* are we reading registers for which a PG lock is necessary? */
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+ pm_pg_lock = (*pos >> 23) & 1;
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+
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+ if (*pos & (1ULL << 62)) {
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+ se_bank = (*pos >> 24) & 0x3FF;
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+ sh_bank = (*pos >> 34) & 0x3FF;
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+ instance_bank = (*pos >> 44) & 0x3FF;
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+
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+ if (se_bank == 0x3FF)
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+ se_bank = 0xFFFFFFFF;
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+ if (sh_bank == 0x3FF)
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+ sh_bank = 0xFFFFFFFF;
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+ if (instance_bank == 0x3FF)
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+ instance_bank = 0xFFFFFFFF;
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+ use_bank = 1;
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+ } else {
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+ use_bank = 0;
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+ }
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+
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+ *pos &= 0x3FFFF;
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+
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+ if (use_bank) {
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+ if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
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+ (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
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+ return -EINVAL;
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+ mutex_lock(&adev->grbm_idx_mutex);
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+ amdgpu_gfx_select_se_sh(adev, se_bank,
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+ sh_bank, instance_bank);
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+ }
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+
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+ if (pm_pg_lock)
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+ mutex_lock(&adev->pm.mutex);
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+
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while (size) {
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while (size) {
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uint32_t value;
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uint32_t value;
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@@ -2661,6 +2696,14 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
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size -= 4;
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size -= 4;
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}
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}
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+ if (use_bank) {
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+ amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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+ mutex_unlock(&adev->grbm_idx_mutex);
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+ }
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+
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+ if (pm_pg_lock)
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+ mutex_unlock(&adev->pm.mutex);
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+
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return result;
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return result;
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}
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}
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