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@@ -1277,7 +1277,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
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/* In the case of a mixed PT the PDE must point to it*/
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if (p->adev->asic_type < CHIP_VEGA10 ||
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nptes != AMDGPU_VM_PTE_COUNT(p->adev) ||
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- p->func == amdgpu_vm_do_copy_ptes ||
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+ p->src ||
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!(flags & AMDGPU_PTE_VALID)) {
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dst = amdgpu_bo_gpu_offset(entry->bo);
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@@ -1294,9 +1294,23 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
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entry->addr = (dst | flags);
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if (use_cpu_update) {
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+ /* In case a huge page is replaced with a system
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+ * memory mapping, p->pages_addr != NULL and
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+ * amdgpu_vm_cpu_set_ptes would try to translate dst
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+ * through amdgpu_vm_map_gart. But dst is already a
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+ * GPU address (of the page table). Disable
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+ * amdgpu_vm_map_gart temporarily.
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+ */
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+ dma_addr_t *tmp;
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+
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+ tmp = p->pages_addr;
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+ p->pages_addr = NULL;
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+
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pd_addr = (unsigned long)amdgpu_bo_kptr(parent->bo);
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pde = pd_addr + (entry - parent->entries) * 8;
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amdgpu_vm_cpu_set_ptes(p, pde, dst, 1, 0, flags);
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+
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+ p->pages_addr = tmp;
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} else {
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if (parent->bo->shadow) {
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pd_addr = amdgpu_bo_gpu_offset(parent->bo->shadow);
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