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@@ -5556,13 +5556,13 @@ static unsigned int skl_cdclk_get_vco(unsigned int freq)
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}
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static void
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-skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
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+skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
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{
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int min_cdclk;
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u32 val;
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/* select the minimum CDCLK before enabling DPLL 0 */
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- if (required_vco == 8640)
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+ if (vco == 8640)
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min_cdclk = 308570;
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else
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min_cdclk = 337500;
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@@ -5585,7 +5585,7 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
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val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
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DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
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val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
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- if (required_vco == 8640)
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+ if (vco == 8640)
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val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
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SKL_DPLL0);
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else
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@@ -5699,13 +5699,13 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
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void skl_init_cdclk(struct drm_i915_private *dev_priv)
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{
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- unsigned int required_vco;
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+ unsigned int vco;
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/* DPLL0 not enabled (happens on early BIOS versions) */
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if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
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/* enable DPLL0 */
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- required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
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- skl_dpll0_enable(dev_priv, required_vco);
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+ vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
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+ skl_dpll0_enable(dev_priv, vco);
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}
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/* set CDCLK to the frequency the BIOS chose */
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