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@@ -9,6 +9,7 @@
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#ifndef _ASM_BCACHE_H
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#define _ASM_BCACHE_H
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+#include <linux/types.h>
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/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
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chipset implemented caches. On machines with other CPUs the CPU does the
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@@ -18,6 +19,9 @@ struct bcache_ops {
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void (*bc_disable)(void);
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void (*bc_wback_inv)(unsigned long page, unsigned long size);
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void (*bc_inv)(unsigned long page, unsigned long size);
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+ void (*bc_prefetch_enable)(void);
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+ void (*bc_prefetch_disable)(void);
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+ bool (*bc_prefetch_is_enabled)(void);
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};
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extern void indy_sc_init(void);
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@@ -46,6 +50,26 @@ static inline void bc_inv(unsigned long page, unsigned long size)
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bcops->bc_inv(page, size);
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}
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+static inline void bc_prefetch_enable(void)
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+{
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+ if (bcops->bc_prefetch_enable)
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+ bcops->bc_prefetch_enable();
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+}
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+
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+static inline void bc_prefetch_disable(void)
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+{
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+ if (bcops->bc_prefetch_disable)
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+ bcops->bc_prefetch_disable();
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+}
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+
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+static inline bool bc_prefetch_is_enabled(void)
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+{
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+ if (bcops->bc_prefetch_is_enabled)
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+ return bcops->bc_prefetch_is_enabled();
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+
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+ return false;
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+}
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+
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#else /* !defined(CONFIG_BOARD_SCACHE) */
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/* Not R4000 / R4400 / R4600 / R5000. */
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@@ -54,6 +78,9 @@ static inline void bc_inv(unsigned long page, unsigned long size)
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#define bc_disable() do { } while (0)
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#define bc_wback_inv(page, size) do { } while (0)
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#define bc_inv(page, size) do { } while (0)
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+#define bc_prefetch_enable() do { } while (0)
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+#define bc_prefetch_disable() do { } while (0)
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+#define bc_prefetch_is_enabled() 0
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#endif /* !defined(CONFIG_BOARD_SCACHE) */
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