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@@ -1164,26 +1164,6 @@ static int tegra_dc_set_timings(struct tegra_dc *dc,
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return 0;
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}
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-int tegra_dc_setup_clock(struct tegra_dc *dc, struct clk *parent,
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- unsigned long pclk, unsigned int div)
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-{
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- u32 value;
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- int err;
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-
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- err = clk_set_parent(dc->clk, parent);
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- if (err < 0) {
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- dev_err(dc->dev, "failed to set parent clock: %d\n", err);
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- return err;
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- }
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-
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- DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
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-
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- value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
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- tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
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-
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- return 0;
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-}
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-
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int tegra_dc_state_setup_clock(struct tegra_dc *dc,
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struct drm_crtc_state *crtc_state,
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struct clk *clk, unsigned long pclk,
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