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@@ -98,6 +98,9 @@ extern int amdgpu_sched_hw_submission;
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#define AMDGPU_MAX_COMPUTE_RINGS 8
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#define AMDGPU_MAX_COMPUTE_RINGS 8
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#define AMDGPU_MAX_VCE_RINGS 2
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#define AMDGPU_MAX_VCE_RINGS 2
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+/* max number of IP instances */
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+#define AMDGPU_MAX_SDMA_INSTANCES 2
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+
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/* number of hw syncs before falling back on blocking */
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/* number of hw syncs before falling back on blocking */
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#define AMDGPU_NUM_SYNCS 4
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#define AMDGPU_NUM_SYNCS 4
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@@ -2057,7 +2060,7 @@ struct amdgpu_device {
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struct amdgpu_gfx gfx;
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struct amdgpu_gfx gfx;
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/* sdma */
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/* sdma */
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- struct amdgpu_sdma sdma[2];
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+ struct amdgpu_sdma sdma[AMDGPU_MAX_SDMA_INSTANCES];
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struct amdgpu_irq_src sdma_trap_irq;
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struct amdgpu_irq_src sdma_trap_irq;
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struct amdgpu_irq_src sdma_illegal_inst_irq;
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struct amdgpu_irq_src sdma_illegal_inst_irq;
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