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@@ -1230,6 +1230,7 @@ static void kv_update_current_ps(struct amdgpu_device *adev,
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pi->current_rps = *rps;
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pi->current_rps = *rps;
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pi->current_ps = *new_ps;
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pi->current_ps = *new_ps;
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pi->current_rps.ps_priv = &pi->current_ps;
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pi->current_rps.ps_priv = &pi->current_ps;
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+ adev->pm.dpm.current_ps = &pi->current_rps;
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}
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}
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static void kv_update_requested_ps(struct amdgpu_device *adev,
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static void kv_update_requested_ps(struct amdgpu_device *adev,
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@@ -1241,6 +1242,7 @@ static void kv_update_requested_ps(struct amdgpu_device *adev,
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pi->requested_rps = *rps;
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pi->requested_rps = *rps;
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pi->requested_ps = *new_ps;
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pi->requested_ps = *new_ps;
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pi->requested_rps.ps_priv = &pi->requested_ps;
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pi->requested_rps.ps_priv = &pi->requested_ps;
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+ adev->pm.dpm.requested_ps = &pi->requested_rps;
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}
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}
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static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
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static void kv_dpm_enable_bapm(struct amdgpu_device *adev, bool enable)
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@@ -3009,7 +3011,6 @@ static int kv_dpm_late_init(void *handle)
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kv_dpm_powergate_samu(adev, true);
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kv_dpm_powergate_samu(adev, true);
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kv_dpm_powergate_vce(adev, true);
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kv_dpm_powergate_vce(adev, true);
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kv_dpm_powergate_uvd(adev, true);
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kv_dpm_powergate_uvd(adev, true);
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-
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return 0;
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return 0;
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}
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}
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@@ -3245,15 +3246,52 @@ static int kv_dpm_set_powergating_state(void *handle,
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return 0;
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return 0;
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}
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}
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+static inline bool kv_are_power_levels_equal(const struct kv_pl *kv_cpl1,
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+ const struct kv_pl *kv_cpl2)
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+{
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+ return ((kv_cpl1->sclk == kv_cpl2->sclk) &&
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+ (kv_cpl1->vddc_index == kv_cpl2->vddc_index) &&
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+ (kv_cpl1->ds_divider_index == kv_cpl2->ds_divider_index) &&
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+ (kv_cpl1->force_nbp_state == kv_cpl2->force_nbp_state));
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+}
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+
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static int kv_check_state_equal(struct amdgpu_device *adev,
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static int kv_check_state_equal(struct amdgpu_device *adev,
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struct amdgpu_ps *cps,
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struct amdgpu_ps *cps,
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struct amdgpu_ps *rps,
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struct amdgpu_ps *rps,
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bool *equal)
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bool *equal)
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{
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{
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- if (equal == NULL)
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+ struct kv_ps *kv_cps;
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+ struct kv_ps *kv_rps;
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+ int i;
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+
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+ if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
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return -EINVAL;
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return -EINVAL;
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- *equal = false;
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+ kv_cps = kv_get_ps(cps);
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+ kv_rps = kv_get_ps(rps);
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+
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+ if (kv_cps == NULL) {
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+ *equal = false;
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+ return 0;
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+ }
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+
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+ if (kv_cps->num_levels != kv_rps->num_levels) {
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+ *equal = false;
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+ return 0;
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+ }
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+
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+ for (i = 0; i < kv_cps->num_levels; i++) {
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+ if (!kv_are_power_levels_equal(&(kv_cps->levels[i]),
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+ &(kv_rps->levels[i]))) {
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+ *equal = false;
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+ return 0;
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+ }
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+ }
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+
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+ /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
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+ *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
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+ *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
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+
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return 0;
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return 0;
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}
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}
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