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@@ -4622,7 +4622,6 @@ static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev)
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queue_mask |= (1ull << i);
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}
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- kiq_ring->ready = true;
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r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8);
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if (r) {
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DRM_ERROR("Failed to lock KIQ (%d).\n", r);
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@@ -4949,26 +4948,33 @@ static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev)
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static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)
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{
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- struct amdgpu_ring *ring = NULL;
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- int r = 0, i;
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-
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- gfx_v8_0_cp_compute_enable(adev, true);
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+ struct amdgpu_ring *ring;
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+ int r;
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ring = &adev->gfx.kiq.ring;
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r = amdgpu_bo_reserve(ring->mqd_obj, false);
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if (unlikely(r != 0))
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- goto done;
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+ return r;
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r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr);
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- if (!r) {
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- r = gfx_v8_0_kiq_init_queue(ring);
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- amdgpu_bo_kunmap(ring->mqd_obj);
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- ring->mqd_ptr = NULL;
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- }
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+ if (unlikely(r != 0))
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+ return r;
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+
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+ gfx_v8_0_kiq_init_queue(ring);
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+ amdgpu_bo_kunmap(ring->mqd_obj);
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+ ring->mqd_ptr = NULL;
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amdgpu_bo_unreserve(ring->mqd_obj);
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- if (r)
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- goto done;
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+ ring->ready = true;
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+ return 0;
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+}
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+
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+static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)
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+{
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+ struct amdgpu_ring *ring = NULL;
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+ int r = 0, i;
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+
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+ gfx_v8_0_cp_compute_enable(adev, true);
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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ring = &adev->gfx.compute_ring[i];
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@@ -5024,14 +5030,17 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
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return r;
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}
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- r = gfx_v8_0_cp_gfx_resume(adev);
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+ r = gfx_v8_0_kiq_resume(adev);
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if (r)
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return r;
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- r = gfx_v8_0_kiq_resume(adev);
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+ r = gfx_v8_0_cp_gfx_resume(adev);
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if (r)
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return r;
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+ r = gfx_v8_0_kcq_resume(adev);
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+ if (r)
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+ return r;
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gfx_v8_0_enable_gui_idle_interrupt(adev, true);
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return 0;
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@@ -5333,10 +5342,6 @@ static int gfx_v8_0_post_soft_reset(void *handle)
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grbm_soft_reset = adev->gfx.grbm_soft_reset;
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srbm_soft_reset = adev->gfx.srbm_soft_reset;
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- if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
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- REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
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- gfx_v8_0_cp_gfx_resume(adev);
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-
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if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
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REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF) ||
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REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC) ||
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@@ -5353,7 +5358,13 @@ static int gfx_v8_0_post_soft_reset(void *handle)
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mutex_unlock(&adev->srbm_mutex);
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}
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gfx_v8_0_kiq_resume(adev);
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+ gfx_v8_0_kcq_resume(adev);
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}
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+
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+ if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP) ||
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+ REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX))
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+ gfx_v8_0_cp_gfx_resume(adev);
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+
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gfx_v8_0_rlc_start(adev);
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return 0;
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