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@@ -167,17 +167,33 @@ void __iomem *omap4_get_l2cache_base(void)
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return l2cache_base;
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return l2cache_base;
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}
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}
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-static void omap4_l2x0_disable(void)
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+static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
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{
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{
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- outer_flush_all();
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- /* Disable PL310 L2 Cache controller */
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- omap_smc1(0x102, 0x0);
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-}
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+ unsigned smc_op;
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-static void omap4_l2x0_set_debug(unsigned long val)
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-{
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- /* Program PL310 L2 Cache controller debug register */
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- omap_smc1(0x100, val);
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+ switch (reg) {
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+ case L2X0_CTRL:
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+ smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
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+ break;
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+
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+ case L2X0_AUX_CTRL:
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+ smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
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+ break;
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+
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+ case L2X0_DEBUG_CTRL:
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+ smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
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+ break;
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+
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+ case L310_PREFETCH_CTRL:
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+ smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
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+ break;
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+
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+ default:
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+ WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
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+ return;
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+ }
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+
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+ omap_smc1(smc_op, val);
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}
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}
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static int __init omap_l2_cache_init(void)
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static int __init omap_l2_cache_init(void)
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@@ -211,18 +227,12 @@ static int __init omap_l2_cache_init(void)
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/* Enable PL310 L2 Cache controller */
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/* Enable PL310 L2 Cache controller */
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omap_smc1(0x102, 0x1);
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omap_smc1(0x102, 0x1);
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+ outer_cache.write_sec = omap4_l2c310_write_sec;
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if (of_have_populated_dt())
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if (of_have_populated_dt())
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l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
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l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
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else
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else
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l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
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l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
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- /*
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- * Override default outer_cache.disable with a OMAP4
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- * specific one
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- */
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- outer_cache.disable = omap4_l2x0_disable;
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- outer_cache.set_debug = omap4_l2x0_set_debug;
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-
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return 0;
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return 0;
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}
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}
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omap_early_initcall(omap_l2_cache_init);
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omap_early_initcall(omap_l2_cache_init);
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