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@@ -264,6 +264,7 @@ enum arm_smmu_s2cr_privcfg {
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#define TTBCR2_SEP_SHIFT 15
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#define TTBCR2_SEP_SHIFT 15
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#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
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#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
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+#define TTBCR2_AS (1 << 4)
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#define TTBRn_ASID_SHIFT 48
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#define TTBRn_ASID_SHIFT 48
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@@ -783,6 +784,8 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
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reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
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reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
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reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
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reg2 = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
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reg2 |= TTBCR2_SEP_UPSTREAM;
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reg2 |= TTBCR2_SEP_UPSTREAM;
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+ if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
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+ reg2 |= TTBCR2_AS;
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}
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}
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if (smmu->version > ARM_SMMU_V1)
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if (smmu->version > ARM_SMMU_V1)
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writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
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writel_relaxed(reg2, cb_base + ARM_SMMU_CB_TTBCR2);
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