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@@ -137,17 +137,26 @@ static int new_mmio_info(struct intel_gvt *gvt,
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return 0;
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}
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-static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg)
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+/**
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+ * intel_gvt_render_mmio_to_ring_id - convert a mmio offset into ring id
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+ * @gvt: a GVT device
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+ * @offset: register offset
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+ *
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+ * Returns:
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+ * Ring ID on success, negative error code if failed.
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+ */
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+int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
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+ unsigned int offset)
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{
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enum intel_engine_id id;
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struct intel_engine_cs *engine;
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- reg &= ~GENMASK(11, 0);
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+ offset &= ~GENMASK(11, 0);
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for_each_engine(engine, gvt->dev_priv, id) {
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- if (engine->mmio_base == reg)
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+ if (engine->mmio_base == offset)
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return id;
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}
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- return -1;
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+ return -ENODEV;
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}
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#define offset_to_fence_num(offset) \
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@@ -1409,7 +1418,7 @@ static int mmio_read_from_hw(struct intel_vgpu *vgpu,
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static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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- int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
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+ int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
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struct intel_vgpu_execlist *execlist;
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u32 data = *(u32 *)p_data;
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int ret = 0;
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@@ -1436,7 +1445,7 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
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void *p_data, unsigned int bytes)
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{
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u32 data = *(u32 *)p_data;
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- int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
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+ int ring_id = intel_gvt_render_mmio_to_ring_id(vgpu->gvt, offset);
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bool enable_execlist;
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write_vreg(vgpu, offset, p_data, bytes);
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