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@@ -1236,20 +1236,13 @@ static bool ar9003_hw_init_cal_soc(struct ath_hw *ah,
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bool txiqcal_done = false;
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bool is_reusable = true, status = true;
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bool run_agc_cal = false, sep_iq_cal = false;
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- u32 rx_delay = 0;
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/* Use chip chainmask only for calibration */
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ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask);
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if (ah->enabled_cals & TX_CL_CAL) {
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- if (caldata && test_bit(TXCLCAL_DONE, &caldata->cal_flags))
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- REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL,
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- AR_PHY_CL_CAL_ENABLE);
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- else {
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- REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL,
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- AR_PHY_CL_CAL_ENABLE);
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- run_agc_cal = true;
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- }
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+ REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
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+ run_agc_cal = true;
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}
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if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
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@@ -1285,15 +1278,6 @@ skip_tx_iqcal:
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REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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}
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- if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
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- rx_delay = REG_READ(ah, AR_PHY_RX_DELAY);
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- /* Disable BB_active */
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- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
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- udelay(5);
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- REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY);
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- REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
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- }
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-
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if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) {
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/* Calibrate the AGC */
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REG_WRITE(ah, AR_PHY_AGC_CONTROL,
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@@ -1306,11 +1290,6 @@ skip_tx_iqcal:
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0, AH_WAIT_TIMEOUT);
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}
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- if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) {
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- REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay);
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- udelay(5);
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- }
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-
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if (!status) {
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ath_dbg(common, CALIBRATE,
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"offset calibration failed to complete in %d ms; noisy environment?\n",
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@@ -1323,8 +1302,6 @@ skip_tx_iqcal:
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else if (caldata && test_bit(TXIQCAL_DONE, &caldata->cal_flags))
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ar9003_hw_tx_iq_cal_reload(ah);
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- ar9003_hw_cl_cal_post_proc(ah, is_reusable);
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-
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/* Revert chainmask to runtime parameters */
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ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
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