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@@ -35,17 +35,19 @@
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*
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*/
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-#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
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+#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
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+#define WIL6210_IRQ_DISABLE_NO_HALP (0xF7FFFFFFUL)
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#define WIL6210_IMC_RX (BIT_DMA_EP_RX_ICR_RX_DONE | \
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BIT_DMA_EP_RX_ICR_RX_HTRSH)
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#define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \
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(~(BIT_DMA_EP_RX_ICR_RX_HTRSH)))
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#define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
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BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
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-#define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \
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- ISR_MISC_MBOX_EVT | \
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- ISR_MISC_FW_ERROR)
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-
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+#define WIL6210_IMC_MISC_NO_HALP (ISR_MISC_FW_READY | \
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+ ISR_MISC_MBOX_EVT | \
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+ ISR_MISC_FW_ERROR)
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+#define WIL6210_IMC_MISC (WIL6210_IMC_MISC_NO_HALP | \
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+ BIT_DMA_EP_MISC_ICR_HALP)
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#define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
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BIT_DMA_PSEUDO_CAUSE_TX | \
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BIT_DMA_PSEUDO_CAUSE_MISC))
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@@ -53,6 +55,7 @@
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#if defined(CONFIG_WIL6210_ISR_COR)
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/* configure to Clear-On-Read mode */
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#define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
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+#define WIL_ICR_ICC_MISC_VALUE (0xF7FFFFFFUL)
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static inline void wil_icr_clear(u32 x, void __iomem *addr)
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{
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@@ -60,6 +63,7 @@ static inline void wil_icr_clear(u32 x, void __iomem *addr)
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#else /* defined(CONFIG_WIL6210_ISR_COR) */
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/* configure to Write-1-to-Clear mode */
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#define WIL_ICR_ICC_VALUE (0UL)
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+#define WIL_ICR_ICC_MISC_VALUE (0UL)
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static inline void wil_icr_clear(u32 x, void __iomem *addr)
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{
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@@ -88,10 +92,21 @@ static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
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WIL6210_IRQ_DISABLE);
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}
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-static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
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+static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
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{
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+ wil_dbg_irq(wil, "%s: mask_halp(%s)\n", __func__,
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+ mask_halp ? "true" : "false");
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+
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
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- WIL6210_IRQ_DISABLE);
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+ mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP);
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+}
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+
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+static void wil6210_mask_halp(struct wil6210_priv *wil)
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+{
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+ wil_dbg_irq(wil, "%s()\n", __func__);
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+
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+ wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
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+ BIT_DMA_EP_MISC_ICR_HALP);
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}
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static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
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@@ -117,10 +132,21 @@ void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
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unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH);
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}
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-static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
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+static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
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{
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+ wil_dbg_irq(wil, "%s: unmask_halp(%s)\n", __func__,
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+ unmask_halp ? "true" : "false");
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+
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
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- WIL6210_IMC_MISC);
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+ unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP);
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+}
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+
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+static void wil6210_unmask_halp(struct wil6210_priv *wil)
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+{
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+ wil_dbg_irq(wil, "%s()\n", __func__);
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+
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+ wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
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+ BIT_DMA_EP_MISC_ICR_HALP);
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}
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static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
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@@ -138,7 +164,7 @@ void wil_mask_irq(struct wil6210_priv *wil)
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wil6210_mask_irq_tx(wil);
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wil6210_mask_irq_rx(wil);
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- wil6210_mask_irq_misc(wil);
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+ wil6210_mask_irq_misc(wil, true);
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wil6210_mask_irq_pseudo(wil);
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}
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@@ -151,12 +177,12 @@ void wil_unmask_irq(struct wil6210_priv *wil)
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wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
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WIL_ICR_ICC_VALUE);
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
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- WIL_ICR_ICC_VALUE);
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+ WIL_ICR_ICC_MISC_VALUE);
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wil6210_unmask_irq_pseudo(wil);
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wil6210_unmask_irq_tx(wil);
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wil6210_unmask_irq_rx(wil);
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- wil6210_unmask_irq_misc(wil);
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+ wil6210_unmask_irq_misc(wil, true);
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}
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void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
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@@ -345,7 +371,7 @@ static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
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return IRQ_NONE;
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}
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- wil6210_mask_irq_misc(wil);
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+ wil6210_mask_irq_misc(wil, false);
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if (isr & ISR_MISC_FW_ERROR) {
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u32 fw_assert_code = wil_r(wil, RGF_FW_ASSERT_CODE);
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@@ -373,12 +399,19 @@ static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
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isr &= ~ISR_MISC_FW_READY;
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}
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+ if (isr & BIT_DMA_EP_MISC_ICR_HALP) {
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+ wil_dbg_irq(wil, "%s: HALP IRQ invoked\n", __func__);
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+ wil6210_mask_halp(wil);
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+ isr &= ~BIT_DMA_EP_MISC_ICR_HALP;
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+ complete(&wil->halp.comp);
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+ }
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+
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wil->isr_misc = isr;
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if (isr) {
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return IRQ_WAKE_THREAD;
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} else {
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- wil6210_unmask_irq_misc(wil);
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+ wil6210_unmask_irq_misc(wil, false);
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return IRQ_HANDLED;
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}
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}
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@@ -415,7 +448,7 @@ static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
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wil->isr_misc = 0;
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- wil6210_unmask_irq_misc(wil);
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+ wil6210_unmask_irq_misc(wil, false);
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return IRQ_HANDLED;
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}
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@@ -557,6 +590,23 @@ void wil6210_clear_irq(struct wil6210_priv *wil)
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wmb(); /* make sure write completed */
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}
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+void wil6210_set_halp(struct wil6210_priv *wil)
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+{
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+ wil_dbg_misc(wil, "%s()\n", __func__);
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+
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+ wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
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+ BIT_DMA_EP_MISC_ICR_HALP);
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+}
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+
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+void wil6210_clear_halp(struct wil6210_priv *wil)
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+{
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+ wil_dbg_misc(wil, "%s()\n", __func__);
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+
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+ wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
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+ BIT_DMA_EP_MISC_ICR_HALP);
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+ wil6210_unmask_halp(wil);
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+}
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+
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int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi)
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{
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int rc;
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