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+/*
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+ * Copyright 2017 Advanced Micro Devices, Inc.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ */
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+
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+#ifndef __AMDGPU_GART_H__
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+#define __AMDGPU_GART_H__
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+
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+#include <linux/types.h>
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+
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+/*
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+ * GART structures, functions & helpers
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+ */
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+struct amdgpu_device;
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+struct amdgpu_bo;
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+struct amdgpu_gart_funcs;
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+
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+#define AMDGPU_GPU_PAGE_SIZE 4096
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+#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
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+#define AMDGPU_GPU_PAGE_SHIFT 12
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+#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
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+
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+struct amdgpu_gart {
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+ dma_addr_t table_addr;
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+ struct amdgpu_bo *robj;
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+ void *ptr;
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+ unsigned num_gpu_pages;
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+ unsigned num_cpu_pages;
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+ unsigned table_size;
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+#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
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+ struct page **pages;
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+#endif
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+ bool ready;
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+
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+ /* Asic default pte flags */
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+ uint64_t gart_pte_flags;
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+
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+ const struct amdgpu_gart_funcs *gart_funcs;
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+};
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+
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+void amdgpu_gart_set_defaults(struct amdgpu_device *adev);
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+int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
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+void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
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+int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
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+void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
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+int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
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+void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
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+int amdgpu_gart_init(struct amdgpu_device *adev);
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+void amdgpu_gart_fini(struct amdgpu_device *adev);
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+int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
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+ int pages);
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+int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
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+ int pages, dma_addr_t *dma_addr, uint64_t flags,
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+ void *dst);
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+int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
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+ int pages, struct page **pagelist,
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+ dma_addr_t *dma_addr, uint64_t flags);
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+
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+#endif
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