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@@ -2103,19 +2103,12 @@ static void execlists_init_reg_state(u32 *reg_state,
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ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
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0);
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- if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
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+ if (ppgtt && USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
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/* 64b PPGTT (48bit canonical)
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* PDP0_DESCRIPTOR contains the base address to PML4 and
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* other PDP Descriptors are ignored.
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*/
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ASSIGN_CTX_PML4(ppgtt, reg_state);
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- } else {
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- /* 32b PPGTT
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- * PDP*_DESCRIPTOR contains the base address of space supported.
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- * With dynamic page allocation, PDPs may not be allocated at
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- * this point. Point the unallocated PDPs to the scratch page
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- */
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- execlists_update_context_pdps(ppgtt, reg_state);
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}
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if (engine->id == RCS) {
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