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@@ -265,8 +265,6 @@ static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
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static inline bool kvm_mwait_in_guest(void)
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{
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- unsigned int eax, ebx, ecx, edx;
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-
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if (!cpu_has(&boot_cpu_data, X86_FEATURE_MWAIT))
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return false;
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@@ -275,29 +273,10 @@ static inline bool kvm_mwait_in_guest(void)
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/* All AMD CPUs have a working MWAIT implementation */
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return true;
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case X86_VENDOR_INTEL:
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- /* Handle Intel below */
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- break;
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+ return !boot_cpu_has_bug(X86_BUG_MONITOR);
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default:
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return false;
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}
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-
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- if (boot_cpu_has_bug(X86_BUG_MONITOR))
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- return false;
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-
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- /*
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- * Intel CPUs without CPUID5_ECX_INTERRUPT_BREAK are problematic as
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- * they would allow guest to stop the CPU completely by disabling
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- * interrupts then invoking MWAIT.
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- */
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- if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
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- return false;
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-
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- cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
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-
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- if (!(ecx & CPUID5_ECX_INTERRUPT_BREAK))
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- return false;
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-
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- return true;
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}
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#endif
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