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@@ -55,12 +55,18 @@
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*
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* For pSeries or server processors:
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* 1. The MMU is off & open firmware is running in real mode.
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- * 2. The kernel is entered at __start
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+ * 2. The primary CPU enters at __start.
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+ * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
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+ * CPUs will enter as directed by "start-cpu" RTAS call, which is
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+ * generic_secondary_smp_init, with PIR in r3.
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+ * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
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+ * directed by the "start-cpu" RTS call, with PIR in r3.
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* -or- For OPAL entry:
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- * 1. The MMU is off, processor in HV mode, primary CPU enters at 0
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- * with device-tree in gpr3. We also get OPAL base in r8 and
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- * entry in r9 for debugging purposes
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- * 2. Secondary processors enter at 0x60 with PIR in gpr3
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+ * 1. The MMU is off, processor in HV mode.
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+ * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
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+ * in r8, and entry in r9 for debugging purposes.
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+ * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
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+ * is at generic_secondary_smp_init, with PIR in r3.
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*
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* For Book3E processors:
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* 1. The MMU is on running in AS0 in a state defined in ePAPR
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