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@@ -3240,16 +3240,14 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
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static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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struct intel_crtc_state *cstate,
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- struct intel_plane *intel_plane,
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+ struct intel_plane_state *intel_pstate,
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uint16_t ddb_allocation,
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int level,
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uint16_t *out_blocks, /* out */
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uint8_t *out_lines /* out */)
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{
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- struct drm_plane *plane = &intel_plane->base;
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- struct drm_framebuffer *fb = plane->state->fb;
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- struct intel_plane_state *intel_pstate =
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- to_intel_plane_state(plane->state);
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+ struct drm_plane_state *pstate = &intel_pstate->base;
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+ struct drm_framebuffer *fb = pstate->fb;
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uint32_t latency = dev_priv->wm.skl_latency[level];
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uint32_t method1, method2;
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uint32_t plane_bytes_per_line, plane_blocks_per_line;
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@@ -3264,7 +3262,7 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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width = drm_rect_width(&intel_pstate->src) >> 16;
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height = drm_rect_height(&intel_pstate->src) >> 16;
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- if (intel_rotation_90_or_270(plane->state->rotation))
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+ if (intel_rotation_90_or_270(pstate->rotation))
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swap(width, height);
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cpp = drm_format_plane_cpp(fb->pixel_format, 0);
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@@ -3284,7 +3282,7 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
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fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
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uint32_t min_scanlines = 4;
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uint32_t y_tile_minimum;
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- if (intel_rotation_90_or_270(plane->state->rotation)) {
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+ if (intel_rotation_90_or_270(pstate->rotation)) {
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int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
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drm_format_plane_cpp(fb->pixel_format, 1) :
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drm_format_plane_cpp(fb->pixel_format, 0);
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@@ -3338,17 +3336,19 @@ static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
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struct drm_device *dev = dev_priv->dev;
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struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
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struct intel_plane *intel_plane;
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+ struct intel_plane_state *intel_pstate;
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uint16_t ddb_blocks;
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enum pipe pipe = intel_crtc->pipe;
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for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
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int i = skl_wm_plane_id(intel_plane);
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+ intel_pstate = to_intel_plane_state(intel_plane->base.state);
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ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
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result->plane_en[i] = skl_compute_plane_wm(dev_priv,
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cstate,
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- intel_plane,
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+ intel_pstate,
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ddb_blocks,
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level,
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&result->plane_res_b[i],
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