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@@ -545,13 +545,12 @@ static void __init setup_xstate_features(void)
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} while (1);
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}
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-static void print_xstate_feature(u64 xstate_mask, const char *desc)
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+static void print_xstate_feature(u64 xstate_mask)
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{
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- if (xfeatures_mask & xstate_mask) {
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- int xstate_feature = fls64(xstate_mask)-1;
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+ const char *feature_name;
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- pr_info("x86/fpu: Supporting XSAVE feature %2d: '%s'\n", xstate_feature, desc);
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- }
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+ if (cpu_has_xfeatures(xstate_mask, &feature_name))
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+ pr_info("x86/fpu: Supporting XSAVE feature 0x%02Lx: '%s'\n", xstate_mask, feature_name);
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}
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/*
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@@ -559,14 +558,14 @@ static void print_xstate_feature(u64 xstate_mask, const char *desc)
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*/
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static void print_xstate_features(void)
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{
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- print_xstate_feature(XSTATE_FP, "x87 floating point registers");
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- print_xstate_feature(XSTATE_SSE, "SSE registers");
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- print_xstate_feature(XSTATE_YMM, "AVX registers");
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- print_xstate_feature(XSTATE_BNDREGS, "MPX bounds registers");
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- print_xstate_feature(XSTATE_BNDCSR, "MPX CSR");
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- print_xstate_feature(XSTATE_OPMASK, "AVX-512 opmask");
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- print_xstate_feature(XSTATE_ZMM_Hi256, "AVX-512 Hi256");
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- print_xstate_feature(XSTATE_Hi16_ZMM, "AVX-512 ZMM_Hi256");
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+ print_xstate_feature(XSTATE_FP);
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+ print_xstate_feature(XSTATE_SSE);
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+ print_xstate_feature(XSTATE_YMM);
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+ print_xstate_feature(XSTATE_BNDREGS);
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+ print_xstate_feature(XSTATE_BNDCSR);
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+ print_xstate_feature(XSTATE_OPMASK);
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+ print_xstate_feature(XSTATE_ZMM_Hi256);
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+ print_xstate_feature(XSTATE_Hi16_ZMM);
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}
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/*
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