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@@ -3864,36 +3864,6 @@ void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
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indirection_rqt[i] = i % num_channels;
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}
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-static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
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-{
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- enum pcie_link_width width;
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- enum pci_bus_speed speed;
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- int err = 0;
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-
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- err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
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- if (err)
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- return err;
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-
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- if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
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- return -EINVAL;
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-
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- switch (speed) {
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- case PCIE_SPEED_2_5GT:
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- *pci_bw = 2500 * width;
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- break;
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- case PCIE_SPEED_5_0GT:
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- *pci_bw = 5000 * width;
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- break;
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- case PCIE_SPEED_8_0GT:
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- *pci_bw = 8000 * width;
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- break;
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- default:
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- return -EINVAL;
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- }
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-
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- return 0;
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-}
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-
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static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
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{
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return (link_speed && pci_bw &&
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@@ -3979,7 +3949,7 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
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params->num_tc = 1;
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mlx5e_get_max_linkspeed(mdev, &link_speed);
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- mlx5e_get_pci_bw(mdev, &pci_bw);
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+ pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
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mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
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link_speed, pci_bw);
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