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@@ -1102,10 +1102,6 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
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struct drm_i915_private *dev_priv = engine->i915;
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struct drm_i915_private *dev_priv = engine->i915;
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uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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- /* WaDisableCtxRestoreArbitration:bxt */
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- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
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- wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
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-
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/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
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/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
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ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
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ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
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if (ret < 0)
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if (ret < 0)
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@@ -1202,10 +1198,6 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
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wa_ctx_emit(batch, index, MI_NOOP);
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wa_ctx_emit(batch, index, MI_NOOP);
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}
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}
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- /* WaDisableCtxRestoreArbitration:bxt */
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- if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
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- wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
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-
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wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
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wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
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return wa_ctx_end(wa_ctx, *offset = index, 1);
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return wa_ctx_end(wa_ctx, *offset = index, 1);
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