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@@ -1090,6 +1090,17 @@ static void update_divide_count(struct kvm_lapic *apic)
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apic->divide_count);
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}
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+static void apic_update_lvtt(struct kvm_lapic *apic)
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+{
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+ u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
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+ apic->lapic_timer.timer_mode_mask;
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+
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+ if (apic->lapic_timer.timer_mode != timer_mode) {
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+ apic->lapic_timer.timer_mode = timer_mode;
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+ hrtimer_cancel(&apic->lapic_timer.timer);
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+ }
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+}
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+
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static void apic_timer_expired(struct kvm_lapic *apic)
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{
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struct kvm_vcpu *vcpu = apic->vcpu;
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@@ -1298,6 +1309,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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apic_set_reg(apic, APIC_LVTT + 0x10 * i,
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lvt_val | APIC_LVT_MASKED);
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}
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+ apic_update_lvtt(apic);
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atomic_set(&apic->lapic_timer.pending, 0);
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}
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@@ -1330,20 +1342,13 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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break;
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- case APIC_LVTT: {
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- u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
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-
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- if (apic->lapic_timer.timer_mode != timer_mode) {
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- apic->lapic_timer.timer_mode = timer_mode;
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- hrtimer_cancel(&apic->lapic_timer.timer);
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- }
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-
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+ case APIC_LVTT:
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if (!kvm_apic_sw_enabled(apic))
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val |= APIC_LVT_MASKED;
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val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
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apic_set_reg(apic, APIC_LVTT, val);
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+ apic_update_lvtt(apic);
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break;
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- }
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case APIC_TMICT:
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if (apic_lvtt_tscdeadline(apic))
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@@ -1576,7 +1581,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
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for (i = 0; i < APIC_LVT_NUM; i++)
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apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
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- apic->lapic_timer.timer_mode = 0;
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+ apic_update_lvtt(apic);
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apic_set_reg(apic, APIC_LVT0,
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SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
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@@ -1802,6 +1807,7 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
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apic_update_ppr(apic);
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hrtimer_cancel(&apic->lapic_timer.timer);
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+ apic_update_lvtt(apic);
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update_divide_count(apic);
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start_apic_timer(apic);
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apic->irr_pending = true;
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