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@@ -414,11 +414,15 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
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dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
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/* return all clocks in KHz */
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/* return all clocks in KHz */
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dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
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dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
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- if (adev->pm.dpm_enabled)
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+ if (adev->pm.dpm_enabled) {
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dev_info.max_engine_clock =
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dev_info.max_engine_clock =
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adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
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adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
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- else
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+ dev_info.max_memory_clock =
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+ adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10;
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+ } else {
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dev_info.max_engine_clock = adev->pm.default_sclk * 10;
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dev_info.max_engine_clock = adev->pm.default_sclk * 10;
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+ dev_info.max_memory_clock = adev->pm.default_mclk * 10;
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+ }
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dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
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dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
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dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
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dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
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adev->gfx.config.max_shader_engines;
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adev->gfx.config.max_shader_engines;
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