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@@ -27,20 +27,16 @@
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#include <asm/mach/map.h>
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#include <asm/memory.h>
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+#include <mach/map.h>
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+
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#include "common.h"
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#include "mfc.h"
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#include "regs-pmu.h"
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-#include "regs-sys.h"
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void __iomem *pmu_base_addr;
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static struct map_desc exynos4_iodesc[] __initdata = {
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{
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- .virtual = (unsigned long)S3C_VA_SYS,
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- .pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
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- .length = SZ_64K,
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- .type = MT_DEVICE,
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- }, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
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.length = SZ_4K,
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@@ -70,11 +66,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
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static struct map_desc exynos5_iodesc[] __initdata = {
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{
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- .virtual = (unsigned long)S3C_VA_SYS,
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- .pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
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- .length = SZ_64K,
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- .type = MT_DEVICE,
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- }, {
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.virtual = (unsigned long)S5P_VA_SROMC,
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.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
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.length = SZ_4K,
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@@ -213,32 +204,6 @@ static void __init exynos_init_irq(void)
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static void __init exynos_dt_machine_init(void)
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{
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- struct device_node *i2c_np;
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- const char *i2c_compat = "samsung,s3c2440-i2c";
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- unsigned int tmp;
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- int id;
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-
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- /*
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- * Exynos5's legacy i2c controller and new high speed i2c
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- * controller have muxed interrupt sources. By default the
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- * interrupts for 4-channel HS-I2C controller are enabled.
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- * If node for first four channels of legacy i2c controller
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- * are available then re-configure the interrupts via the
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- * system register.
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- */
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- if (soc_is_exynos5()) {
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- for_each_compatible_node(i2c_np, NULL, i2c_compat) {
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- if (of_device_is_available(i2c_np)) {
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- id = of_alias_get_id(i2c_np, "i2c");
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- if (id < 4) {
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- tmp = readl(EXYNOS5_SYS_I2C_CFG);
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- writel(tmp & ~(0x1 << id),
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- EXYNOS5_SYS_I2C_CFG);
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- }
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- }
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- }
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- }
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-
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/*
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* This is called from smp_prepare_cpus if we've built for SMP, but
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* we still need to set it up for PM and firmware ops if not.
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