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@@ -15,7 +15,9 @@
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*/
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#include <linux/io.h>
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+#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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+#include <linux/regmap.h>
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#include <linux/clk/zynq.h>
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#include "common.h"
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@@ -29,7 +31,56 @@
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#define SLCR_A9_CPU_CLKSTOP 0x10
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#define SLCR_A9_CPU_RST 0x1
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-void __iomem *zynq_slcr_base;
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+static void __iomem *zynq_slcr_base;
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+static struct regmap *zynq_slcr_regmap;
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+
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+/**
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+ * zynq_slcr_write - Write to a register in SLCR block
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+ *
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+ * @val: Value to write to the register
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+ * @offset: Register offset in SLCR block
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+ *
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+ * Return: a negative value on error, 0 on success
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+ */
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+static int zynq_slcr_write(u32 val, u32 offset)
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+{
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+ if (!zynq_slcr_regmap) {
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+ writel(val, zynq_slcr_base + offset);
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+ return 0;
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+ }
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+
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+ return regmap_write(zynq_slcr_regmap, offset, val);
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+}
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+
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+/**
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+ * zynq_slcr_read - Read a register in SLCR block
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+ *
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+ * @val: Pointer to value to be read from SLCR
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+ * @offset: Register offset in SLCR block
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+ *
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+ * Return: a negative value on error, 0 on success
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+ */
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+static int zynq_slcr_read(u32 *val, u32 offset)
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+{
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+ if (zynq_slcr_regmap)
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+ return regmap_read(zynq_slcr_regmap, offset, val);
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+
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+ *val = readl(zynq_slcr_base + offset);
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+
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+ return 0;
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+}
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+
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+/**
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+ * zynq_slcr_unlock - Unlock SLCR registers
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+ *
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+ * Return: a negative value on error, 0 on success
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+ */
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+static inline int zynq_slcr_unlock(void)
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+{
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+ zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
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+
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+ return 0;
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+}
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/**
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* zynq_slcr_system_reset - Reset the entire system.
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@@ -43,16 +94,16 @@ void zynq_slcr_system_reset(void)
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* Note that this seems to require raw i/o
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* functions or there's a lockup?
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*/
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- writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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+ zynq_slcr_unlock();
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* the FSBL not loading the bitstream after soft-reboot
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* This is a temporary solution until we know more.
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*/
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- reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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- writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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- writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
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+ zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
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+ zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
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+ zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
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}
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/**
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@@ -61,11 +112,13 @@ void zynq_slcr_system_reset(void)
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*/
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void zynq_slcr_cpu_start(int cpu)
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{
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- u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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+ u32 reg;
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+
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+ zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg &= ~(SLCR_A9_CPU_RST << cpu);
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- writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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+ zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
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- writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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+ zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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/**
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@@ -74,18 +127,39 @@ void zynq_slcr_cpu_start(int cpu)
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*/
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void zynq_slcr_cpu_stop(int cpu)
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{
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- u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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+ u32 reg;
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+
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+ zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
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- writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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+ zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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/**
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- * zynq_slcr_init
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- * Returns 0 on success, negative errno otherwise.
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+ * zynq_slcr_init - Regular slcr driver init
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+ *
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+ * Return: 0 on success, negative errno otherwise.
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*
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* Called early during boot from platform code to remap SLCR area.
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*/
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int __init zynq_slcr_init(void)
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+{
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+ zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
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+ if (IS_ERR(zynq_slcr_regmap)) {
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+ pr_err("%s: failed to find zynq-slcr\n", __func__);
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+ return -ENODEV;
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+ }
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+
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+ return 0;
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+}
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+
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+/**
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+ * zynq_early_slcr_init - Early slcr init function
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+ *
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+ * Return: 0 on success, negative errno otherwise.
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+ *
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+ * Called very early during boot from platform code to unlock SLCR.
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+ */
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+int __init zynq_early_slcr_init(void)
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{
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struct device_node *np;
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@@ -101,13 +175,13 @@ int __init zynq_slcr_init(void)
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BUG();
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}
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+ np->data = (__force void *)zynq_slcr_base;
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+
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/* unlock the SLCR so that registers can be changed */
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- writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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+ zynq_slcr_unlock();
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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- zynq_clock_init(zynq_slcr_base);
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-
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of_node_put(np);
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return 0;
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Arnd Bergmann