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@@ -578,7 +578,7 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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bo->adev->vram_pin_size += amdgpu_bo_size(bo);
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bo->adev->vram_pin_size += amdgpu_bo_size(bo);
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if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
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if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
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bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
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bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
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- } else {
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+ } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
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bo->adev->gart_pin_size += amdgpu_bo_size(bo);
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bo->adev->gart_pin_size += amdgpu_bo_size(bo);
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}
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}
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