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@@ -314,7 +314,25 @@ static int dwc3_core_init(struct dwc3 *dwc)
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switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
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case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
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- reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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+ /**
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+ * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
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+ * issue which would cause xHCI compliance tests to fail.
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+ *
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+ * Because of that we cannot enable clock gating on such
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+ * configurations.
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+ *
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+ * Refers to:
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+ *
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+ * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
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+ * SOF/ITP Mode Used
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+ */
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+ if ((dwc->dr_mode == USB_DR_MODE_HOST ||
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+ dwc->dr_mode == USB_DR_MODE_OTG) &&
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+ (dwc->revision >= DWC3_REVISION_210A &&
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+ dwc->revision <= DWC3_REVISION_250A))
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+ reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
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+ else
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+ reg &= ~DWC3_GCTL_DSBLCLKGTNG;
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break;
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default:
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dev_dbg(dwc->dev, "No power optimization available\n");
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@@ -479,6 +497,14 @@ static int dwc3_probe(struct platform_device *pdev)
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goto err0;
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}
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+ if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
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+ dwc->dr_mode = USB_DR_MODE_HOST;
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+ else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
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+ dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
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+
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+ if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
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+ dwc->dr_mode = USB_DR_MODE_OTG;
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+
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ret = dwc3_core_init(dwc);
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if (ret) {
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dev_err(dev, "failed to initialize core\n");
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@@ -494,14 +520,6 @@ static int dwc3_probe(struct platform_device *pdev)
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goto err1;
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}
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- if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
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- dwc->dr_mode = USB_DR_MODE_HOST;
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- else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
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- dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
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-
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- if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
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- dwc->dr_mode = USB_DR_MODE_OTG;
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-
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switch (dwc->dr_mode) {
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case USB_DR_MODE_PERIPHERAL:
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dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
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