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@@ -165,6 +165,26 @@ static void sxgbe_core_set_speed(void __iomem *ioaddr, unsigned char speed)
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writel(tx_cfg, ioaddr + SXGBE_CORE_TX_CONFIG_REG);
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}
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+static void sxgbe_core_enable_rxqueue(void __iomem *ioaddr, int queue_num)
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+{
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+ u32 reg_val;
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+
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+ reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);
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+ reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);
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+ reg_val |= SXGBE_CORE_RXQ_ENABLE;
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+ writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
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+}
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+
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+static void sxgbe_core_disable_rxqueue(void __iomem *ioaddr, int queue_num)
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+{
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+ u32 reg_val;
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+
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+ reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG);
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+ reg_val &= ~(SXGBE_CORE_RXQ_ENABLE_MASK << queue_num);
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+ reg_val |= SXGBE_CORE_RXQ_DISABLE;
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+ writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG);
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+}
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+
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static void sxgbe_set_eee_mode(void __iomem *ioaddr)
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{
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u32 ctrl;
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@@ -254,6 +274,8 @@ static const struct sxgbe_core_ops core_ops = {
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.set_eee_pls = sxgbe_set_eee_pls,
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.enable_rx_csum = sxgbe_enable_rx_csum,
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.disable_rx_csum = sxgbe_disable_rx_csum,
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+ .enable_rxqueue = sxgbe_core_enable_rxqueue,
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+ .disable_rxqueue = sxgbe_core_disable_rxqueue,
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};
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const struct sxgbe_core_ops *sxgbe_get_core_ops(void)
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