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@@ -27,6 +27,7 @@
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#include "amdgpu_gfx.h"
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#include "amdgpu_gfx.h"
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#include "soc15.h"
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#include "soc15.h"
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#include "soc15d.h"
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#include "soc15d.h"
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+#include "amdgpu_atomfirmware.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_offset.h"
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#include "gc/gc_9_0_sh_mask.h"
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#include "gc/gc_9_0_sh_mask.h"
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@@ -1113,9 +1114,10 @@ static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
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.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
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.select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
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};
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};
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-static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
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+static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
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{
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{
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u32 gb_addr_config;
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u32 gb_addr_config;
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+ int err;
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adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
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adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
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@@ -1146,6 +1148,10 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
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gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
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gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
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gb_addr_config &= ~0xf3e777ff;
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gb_addr_config &= ~0xf3e777ff;
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gb_addr_config |= 0x22014042;
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gb_addr_config |= 0x22014042;
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+ /* check vbios table if gpu info is not available */
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+ err = amdgpu_atomfirmware_get_gfx_info(adev);
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+ if (err)
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+ return err;
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break;
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break;
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case CHIP_RAVEN:
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case CHIP_RAVEN:
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adev->gfx.config.max_hw_contexts = 8;
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adev->gfx.config.max_hw_contexts = 8;
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@@ -1196,6 +1202,8 @@ static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
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adev->gfx.config.gb_addr_config,
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adev->gfx.config.gb_addr_config,
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GB_ADDR_CONFIG,
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GB_ADDR_CONFIG,
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PIPE_INTERLEAVE_SIZE));
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PIPE_INTERLEAVE_SIZE));
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+
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+ return 0;
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}
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}
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static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
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static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
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@@ -1557,7 +1565,9 @@ static int gfx_v9_0_sw_init(void *handle)
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adev->gfx.ce_ram_size = 0x8000;
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adev->gfx.ce_ram_size = 0x8000;
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- gfx_v9_0_gpu_early_init(adev);
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+ r = gfx_v9_0_gpu_early_init(adev);
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+ if (r)
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+ return r;
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r = gfx_v9_0_ngg_init(adev);
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r = gfx_v9_0_ngg_init(adev);
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if (r)
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if (r)
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