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@@ -137,6 +137,31 @@ static int omap_dm_timer_reset(struct omap_dm_timer *timer)
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return 0;
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}
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+static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer)
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+{
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+ int ret;
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+ struct clk *parent;
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+
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+ /*
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+ * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
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+ * do not call clk_get() for these devices.
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+ */
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+ if (!timer->fclk)
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+ return -ENODEV;
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+
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+ parent = clk_get(&timer->pdev->dev, NULL);
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+ if (IS_ERR(parent))
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+ return -ENODEV;
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+
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+ ret = clk_set_parent(timer->fclk, parent);
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+ if (ret < 0)
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+ pr_err("%s: failed to set parent\n", __func__);
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+
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+ clk_put(parent);
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+
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+ return ret;
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+}
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+
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static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
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{
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int rc;
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@@ -166,7 +191,11 @@ static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
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__omap_dm_timer_enable_posted(timer);
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omap_dm_timer_disable(timer);
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- return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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+ rc = omap_dm_timer_of_set_source(timer);
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+ if (rc == -ENODEV)
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+ return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
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+
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+ return rc;
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}
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static inline u32 omap_dm_timer_reserved_systimer(int id)
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