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@@ -40,6 +40,7 @@
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typedef u32 ixgbe_link_speed;
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typedef u32 ixgbe_link_speed;
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#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
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#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
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#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
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#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
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+#define IXGBE_LINK_SPEED_100_FULL 0x0008
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#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
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#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
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#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
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#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
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@@ -48,6 +49,7 @@ typedef u32 ixgbe_link_speed;
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#define IXGBE_LINKS_SPEED_82599 0x30000000
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#define IXGBE_LINKS_SPEED_82599 0x30000000
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#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
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#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
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#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
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#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
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+#define IXGBE_LINKS_SPEED_100_82599 0x10000000
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/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
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/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
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#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
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#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
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