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@@ -5146,6 +5146,180 @@ int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
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}
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EXPORT_SYMBOL(pcie_get_minimum_link);
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+/**
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+ * pcie_bandwidth_available - determine minimum link settings of a PCIe
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+ * device and its bandwidth limitation
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+ * @dev: PCI device to query
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+ * @limiting_dev: storage for device causing the bandwidth limitation
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+ * @speed: storage for speed of limiting device
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+ * @width: storage for width of limiting device
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+ *
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+ * Walk up the PCI device chain and find the point where the minimum
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+ * bandwidth is available. Return the bandwidth available there and (if
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+ * limiting_dev, speed, and width pointers are supplied) information about
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+ * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
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+ * raw bandwidth.
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+ */
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+u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
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+ enum pci_bus_speed *speed,
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+ enum pcie_link_width *width)
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+{
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+ u16 lnksta;
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+ enum pci_bus_speed next_speed;
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+ enum pcie_link_width next_width;
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+ u32 bw, next_bw;
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+
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+ if (speed)
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+ *speed = PCI_SPEED_UNKNOWN;
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+ if (width)
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+ *width = PCIE_LNK_WIDTH_UNKNOWN;
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+
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+ bw = 0;
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+
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+ while (dev) {
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+ pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
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+
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+ next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
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+ next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
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+ PCI_EXP_LNKSTA_NLW_SHIFT;
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+
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+ next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
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+
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+ /* Check if current device limits the total bandwidth */
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+ if (!bw || next_bw <= bw) {
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+ bw = next_bw;
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+
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+ if (limiting_dev)
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+ *limiting_dev = dev;
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+ if (speed)
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+ *speed = next_speed;
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+ if (width)
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+ *width = next_width;
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+ }
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+
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+ dev = pci_upstream_bridge(dev);
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+ }
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+
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+ return bw;
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+}
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+EXPORT_SYMBOL(pcie_bandwidth_available);
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+
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+/**
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+ * pcie_get_speed_cap - query for the PCI device's link speed capability
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+ * @dev: PCI device to query
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+ *
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+ * Query the PCI device speed capability. Return the maximum link speed
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+ * supported by the device.
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+ */
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+enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
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+{
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+ u32 lnkcap2, lnkcap;
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+
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+ /*
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+ * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
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+ * Speeds Vector in Link Capabilities 2 when supported, falling
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+ * back to Max Link Speed in Link Capabilities otherwise.
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+ */
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+ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
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+ if (lnkcap2) { /* PCIe r3.0-compliant */
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+ if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
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+ return PCIE_SPEED_16_0GT;
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+ else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
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+ return PCIE_SPEED_8_0GT;
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+ else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
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+ return PCIE_SPEED_5_0GT;
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+ else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
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+ return PCIE_SPEED_2_5GT;
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+ return PCI_SPEED_UNKNOWN;
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+ }
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+
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+ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
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+ if (lnkcap) {
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+ if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
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+ return PCIE_SPEED_16_0GT;
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+ else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
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+ return PCIE_SPEED_8_0GT;
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+ else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
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+ return PCIE_SPEED_5_0GT;
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+ else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
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+ return PCIE_SPEED_2_5GT;
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+ }
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+
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+ return PCI_SPEED_UNKNOWN;
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+}
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+
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+/**
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+ * pcie_get_width_cap - query for the PCI device's link width capability
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+ * @dev: PCI device to query
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+ *
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+ * Query the PCI device width capability. Return the maximum link width
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+ * supported by the device.
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+ */
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+enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
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+{
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+ u32 lnkcap;
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+
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+ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
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+ if (lnkcap)
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+ return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
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+
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+ return PCIE_LNK_WIDTH_UNKNOWN;
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+}
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+
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+/**
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+ * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
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+ * @dev: PCI device
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+ * @speed: storage for link speed
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+ * @width: storage for link width
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+ *
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+ * Calculate a PCI device's link bandwidth by querying for its link speed
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+ * and width, multiplying them, and applying encoding overhead. The result
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+ * is in Mb/s, i.e., megabits/second of raw bandwidth.
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+ */
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+u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
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+ enum pcie_link_width *width)
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+{
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+ *speed = pcie_get_speed_cap(dev);
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+ *width = pcie_get_width_cap(dev);
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+
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+ if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
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+ return 0;
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+
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+ return *width * PCIE_SPEED2MBS_ENC(*speed);
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+}
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+
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+/**
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+ * pcie_print_link_status - Report the PCI device's link speed and width
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+ * @dev: PCI device to query
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+ *
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+ * Report the available bandwidth at the device. If this is less than the
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+ * device is capable of, report the device's maximum possible bandwidth and
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+ * the upstream link that limits its performance to less than that.
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+ */
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+void pcie_print_link_status(struct pci_dev *dev)
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+{
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+ enum pcie_link_width width, width_cap;
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+ enum pci_bus_speed speed, speed_cap;
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+ struct pci_dev *limiting_dev = NULL;
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+ u32 bw_avail, bw_cap;
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+
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+ bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
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+ bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
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+
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+ if (bw_avail >= bw_cap)
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+ pci_info(dev, "%u.%03u Gb/s available bandwidth (%s x%d link)\n",
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+ bw_cap / 1000, bw_cap % 1000,
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+ PCIE_SPEED2STR(speed_cap), width_cap);
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+ else
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+ pci_info(dev, "%u.%03u Gb/s available bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
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+ bw_avail / 1000, bw_avail % 1000,
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+ PCIE_SPEED2STR(speed), width,
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+ limiting_dev ? pci_name(limiting_dev) : "<unknown>",
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+ bw_cap / 1000, bw_cap % 1000,
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+ PCIE_SPEED2STR(speed_cap), width_cap);
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+}
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+EXPORT_SYMBOL(pcie_print_link_status);
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+
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/**
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* pci_select_bars - Make BAR mask from the type of resource
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* @dev: the PCI device for which BAR mask is made
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Bjorn Helgaas